DP83950B datasheet(28/80 Pages) NSC

28 / 80 page

50 Functional Description (Continued)

The second method of

PORT N or M identification avoids

this problem This second technique relies on an external

parallel arbiter which monitors all of the RIC’s ACKO signals

and responds to the RIC with the highest priority In this

scheme each RIC is assigned with a priority level One

method of doing this is to assign a priority number which

reflects the position of a RIC board on the repeater back-

plane ie its slot number When a RIC experiences receive

activity and the repeater system is in the

IDLE state the RIC

board will assert ACKO External arbitration logic drives the

identification number onto an arbitration bus and the RIC

containing

PORT N will be identified An identical procedure

is used in the

TRANSMIT COLLISION state to identify

PORT M This parallel means of arbitration is not subject to

the problems caused by missing boards ie empty slots in

the backplane The logic associated with asserting this arbi-

tration vector in the various packet repetition scenarios

could be implemented in programmable logic type devices

To perform

PORT N or M arbitration both of the above

methods employ the same signals ACKI ACKO and ACTN

The Inter-RIC bus allows multi-RIC operations to be per-

formed in exactly the same manner as if there is only a

single RIC in the system The simplest way to describe the

operation of Inter-RIC bus is to see how it is used in a num-

ber of common packet repetition scenarios Throughout this

description the RICs are presumed to be operating in exter-

nal transceiver mode This is advantageous for the explana-

tion since the receive transmit and collision signals from

each network segment are observable In internal transceiv-

er mode this is not the case since the collision signal for the

non-AUI ports is derived by the transceivers inside the RIC

53 EXAMPLES OF PACKET REPETITION SCENARIOS

Data Repetition

The simplest packet operation performed over the Inter-RIC

Bus is data repetition In this operation a data packet is

received at one port and transmitted to all other segments

The first task to be performed is

PORT N identification This

is an arbitration process performed by the Port State Ma-

chines in the system In situations where two or more ports

simultaneously receive packets the Inter-RIC bus operates

by choosing one of the active ports and forcing the others to

transmit data This is done to faithfully follow the IEEE spec-

ification’s allowed exit paths from the

IDLE state ie to the

SEND PREAMBLE PATTERN or RECEIVE COLLISION

states

The packet begins with a preamble pattern derived from the

RIC’s on chip jampreamble generator The data received

PORT N is directed through the receive multiplexor to the

PLL decoder Once phase lock has been achieved the de-

coded data in NRZ format with its associated clock and

enable signals are asserted onto the IRD IRE and IRC Inter-

RIC bus lines This serial data stream is received from the

bus by all RICs in the repeater and directed to their Elasticity

Buffers Logic circuits monitor the data stream and look for

the Start of Frame Delimiter (SFD) When this has been

detected data is loaded into the elasticity buffer for later

transmission This will occur when sufficient preamble has

been transmitted and certain internal state machine opera-

tions have been fulfilled

Figure 54 shows two RICs A and B daisy chained together

with RIC A positioned at the top of the chain A packet is

received at port B1 of RIC B and is then repeated by the

other ports in the system

Figure 55 shows the functional

timing diagram for this packet repetition represented by the

signals shown in

Figure 54 In this example only two ports

in the system are shown obviously the other ports also re-

peat the packet It also indicates the operation of the RICs’

state machines in so far as can be seen by observing the

Inter-RIC bus For reference the repeater’s state transitions

are shown in terms of the states defined by the IEEE specifi-

cation The location ie which port it is of

PORT N is also

shown The following section describes the repeater and

Inter-RIC bus transitions shown in

Figure 55

The repeater is stimulated into activity by the data signal

received by port B1 The RICs in the system are alerted to

forthcoming repeater operation by the falling edges on the

ACKI ACKO daisy chain and the ACTN bus signal Following

a defined start up delay the repeater moves to the

SEND

PREAMBLE state The RIC system utilizes the start up de-

lay to perform port arbitration When packet transmission

begins the RIC system enter the REPEAT state

The expected for normal packet repetition sequence of re-

peater states

SEND PREAMBLE SEND SFD and SEND

DATA is followed but is not visible upon the Inter-RIC bus

They are merged together into a single REPEAT state This

is also true for the

WAIT and IDLE states they appear as a

combined Inter-RIC bus IDLE state

Once a repeat operation has begun ie the repeater leaves

the

IDLE state It is required to transmit at least 96 bits of

data or jampreamble onto its network segments If the du-

ration of the received signal from

PORT N is smaller than 96

bits the repeater transitions to the

RECEIVE COLLISION

state (described later) This behavior is known as fragment

extension

After the packet data has been repeated including the emp-

tying of the RICs’ elasticity buffers the RIC performs the

Tw1 transmit recovery operation This is performed during

the

WAIT state shown in the repeater state diagram

DP83950B Datasheet(PDF) 28 Page - National Semiconductor (TI)

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