DP83950B datasheet(65/80 Pages) NSC

65 / 80 page

80 RIC Registers (Continued)

RIC Address Register (Page 0H Address 17H)

This register may be used to differentiate between RICs in a multi-RIC repeater system The contents of this register form part of

the information available through the management bus

res

Packet Compress Decode Register (Page 0H Address 18H)

This register is used to determine the number of bytes in the data field of a packet which are transferred over the management

bus when the packet compress option is employed The register bits perform the function of a direct binary decode Thus up to

255 bytes of data may be transferred over the management bus if packet compression is selected

PCD7

PCD6

PCD5

PCD4

PCD3

PCD2

PCD1

PCD0

Inter Frame Gap Threshold Select Register (Page 0H Address 1FH)

This register is used to configure the hub management interface to provide a certain minimum inter frame gap between packets

transmitted over the management bus The value written to this register plus one is the magnitude in bit times of the minimum

IFG allowed on the management bus

IFGT7

IFGT6

IFGT5

IFGT4

IFGT3

IFGT2

IFGT1

IFGT0

Port Event Record Registers (Page 1H Address 11H to 1DH)

These registers hold the recorded events for the specified RIC port The flags are cleared when the register is read

BDLNK

PART

OWC

NSFD

PLER

ELBER

JAB

Bit

Symbol

Description

JAB

JABBER

A Jabber Protect event has occurred

ELBER

ELASTICITY BUFFER ERROR

A Elasticity Buffer Error has occurred

PLER

PHASE LOCK ERROR

A Phase Lock Error event has occurred

NSFD

NON SFD

A Non SFD packet event has occurred

SHORT EVENT

A Short event has occurred

OWC

OUT OF WINDOW COLLISION

An out of window collision event has occurred

PART

PARTITION

A partition event has occurred

BDLNK

BAD LINK

A link failure event has occurred

Port Event Count Register (Pages 2H and 3H)

The Event Count (EC) register shows the instantaneous value of the specified port’s 16-bit counter The counter increments

when an enabled event occurs The counter may be cleared when it is read and prevented from rolling over when the maximum

count is reached by setting the appropriate control bits in the Upper Event Count mask register Since the RIC’s processor port

is octal and the counters are 16 bits long a temporary holding register is employed for register reads When one of the counters

is read either high or low byte first all 16 bits of the counter are transferred to a holding register Provided the next read cycle to

the counter array accesses the same counter’s other byte then the read cycle accesses the holding register This avoids the

problem of events occurring in between the two processor reads and indicating a false count value In order to enter a new value

to the holding register a different counter must be accessed or the same counter byte must be re-read

Lower Byte

EC7

EC6

EC5

EC4

EC3

EC2

EC1

EC0

Upper Byte

EC15

EC14

EC13

EC12

EC11

EC10

EC9

EC8

DP83950B Datasheet(PDF) 65 Page - National Semiconductor (TI)

DP83950B Datasheet(HTML) 65 Page - National Semiconductor (TI)

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