DP83950B datasheet(59/80 Pages) NSC

59 / 80 page

80 RIC Registers (Continued)

RIC Configuration Register (Address 0EH)

This register displays the state of a number of RIC configuration bits loaded during the Mode Load operation

MINMAX

DPART

TX ONLY

OWCE

LPPART

CCLIM

Tw2

resv

Bit

Symbol

Description

resv

RESERVED FOR FUTURE USE

Value set at logic one

Tw2

CARRIER RECOVERY TIME

0 Tw2 set at 5 bits

1 Tw2 set at 3 bits

CCLIM

CONSECUTIVE COLLISION LIMIT

0 Consecutive collision limit set at 63 collisions

1 Consecutive collision limit set at 31 collisions

LPPART

LOOPBACK PARTITION

0 Partitioning upon lack of loopback from transceivers is enabled

1 Partitioning upon lack of loopback from transceivers is disabled

OWCE

OUT OF WINDOW COLLISION ENABLE

0 Out of window collisions are treated as in window collisions by the segment partition state

machines

1 Out of window collisions are treated as out of window collisions by the segment partition state

machines

TXONLY

ONLY RECONNECT UPON SEGMENT TRANSMISSION

0 A segment will only be reconnected to the network if a packet transmitted by the RIC onto that

segment fulfills the requirements of the segment reconnection algorithm

1 A segment will be reconnected to the network by any packet on the network which fullfills the

requirements of the segment reconnection algorithm

DPART

DISABLE PARTITION

0 Partitioning of ports by on-chip algorithms is prevented

1 Partitioning of ports by on-chip algorithms is enabled

MINMAX

MINIMUMMAXIMUM DISPLAY MODE

0 LED display set in minimum display mode

1 LED display set in maximum display mode

DP83950B Datasheet(PDF) 59 Page - National Semiconductor (TI)

DP83950B Datasheet(HTML) 59 Page - National Semiconductor (TI)

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