TMS320DM641 datasheet(138/171 Pages) TI

138 / 171 page

Multichannel Buffered Serial Port (McBSP)

138

June 2003 − Revised August 2004

SPRS222C

4.12.2

McBSP Electrical Data/Timing

4.12.2.1 Multichannel Buffered Serial Port (McBSP) Timing

Table 4−43. Timing Requirements for McBSP† (see Figure 4−42)

NO.

−400

−500

−600

UNIT

MIN

MAX

tc(CKRX)

Cycle time, CLKR/X

CLKR/X ext

4P or 6.67‡§

tw(CKRX)

Pulse duration, CLKR/X high or CLKR/X low

CLKR/X ext

0.5tc(CKRX) − 1¶

tsu(FRH-CKRL)

Setup time, external FSR high before CLKR low

CLKR int

tsu(FRH-CKRL)

Setup time, external FSR high before CLKR low

CLKR ext

1.3

th(CKRL-FRH)

Hold time, external FSR high after CLKR low

CLKR int

th(CKRL-FRH)

Hold time, external FSR high after CLKR low

CLKR ext

tsu(DRV-CKRL)

Setup time, DR valid before CLKR low

CLKR int

tsu(DRV-CKRL)

Setup time, DR valid before CLKR low

CLKR ext

0.9

th(CKRL-DRV)

Hold time, DR valid after CLKR low

CLKR int

th(CKRL-DRV)

Hold time, DR valid after CLKR low

CLKR ext

3.1

tsu(FXH-CKXL)

Setup time, external FSX high before CLKX low

CLKX int

tsu(FXH-CKXL)

Setup time, external FSX high before CLKX low

CLKX ext

1.3

th(CKXL-FXH)

Hold time, external FSX high after CLKX low

CLKX int

th(CKXL-FXH)

Hold time, external FSX high after CLKX low

CLKX ext

† CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.

‡ P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.

§ Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. The

minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing

requirements.

¶ This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.

TMS320DM641 Datasheet(PDF) 138 Page - Texas Instruments

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