TUSB5052 datasheet(51/82 Pages) TI

51 / 82 page

7−3

7.1.4

FCRL[2:1]: UART Flow Control Registers (2 Registers)

These registers provide the flow-control modes of operation (see Table 7−2 and Table 7−3).

485E

DTR

RTS

RXOF

DSR

CTS

TXOA

TXOF

R/W

BIT

NAME

RESET

FUNCTION

TXOF

This bit controls the transmitter Xon/Xoff flow control.

TXOF

TXOF = 0

Disables transmitter Xon/Xoff flow control

TXOF = 1

Enables transmitter Xon/Xoff flow control

TXOA

This bit controls the transmitter Xon-on-any/Xoff flow control.

TXOA

TXOA = 0

Disables the transmitter Xon-on-any/Xoff flow control

TXOA = 1

Enables the transmitter Xon-on-any/Xoff flow control

CTS

Transmitter CTS flow-control enable bit.

CTS

CTS = 0

Disables transmitter CTS flow control

CTS = 1

CTS flow control is enabled, i.e., when CTS input pin is high, transmission is halted; when CTS pin is

low, transmission resumes.

DSR

Transmitter DSR flow control enable bit.

DSR

DSR = 0

Disables transmitter DSR flow control

DSR = 1

DSR flow control is enabled, i.e., when DSR input pin is high, transmission is halted; when DSR pin is

low, transmission resumes.

RXOF

This bit controls the receiver Xon/Xoff flow control.

RXOF

RXOF = 0

Receiver does not attempt to match Xon/Xoff characters.

RXOF = 1

Receiver searches for Xon/Xoff characters.

RTS

Receiver RTS flow control enable bit

RTS

RTS = 0

Disables receiver RTS flow control

RTS = 1

Receiver RTS flow control is enabled. RTS output pin goes high when the receiver FIFO HALT

trigger level is reached; it goes low, when the receiver FIFO RESTORE receiving trigger level is

reached.

DTR

Receiver DTR flow control enable bit

DTR

DTR = 0

Disables receiver DTR flow control

DDT = 1

Receiver DDT flow control is enabled. DDT output pin goes high when the receiver FIFO HALT

trigger level is reached; it goes low when the receiver FIFO RESTORE receiving trigger level is

reached.

485E

RHEA485 enable bit. This bit is used to configure the UARTs to control external RS485 transceivers. When config-

ured in half-duplex mode, RTS and DTR are used to enable the RS485 driver and receiver (see Figure 12−2).

485E = 0

UART is in normal operation mode (full duplex).

485E = 1

The UART is in RS485 mode. In this mode RTS and DTR are active with opposite polarity (when

RTS = 0, DTR = 1). When the DMA is ready to transmit, it drives RTS = 1 (and DTR = 0) 2-bit-time

before transmission starts. When DMA terminates the transmission, it drives RTS = 0 (and

DTR = 1) as soon as possible after transmission stops. When 485E is set to 1, the DTR and RTS bits

in the MCR register have no effect.

TUSB5052 Datasheet(PDF) 51 Page - Texas Instruments

TUSB5052 Datasheet(HTML) 51 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82

Datasheet Download

Link URL