TUSB5052 datasheet(56/82 Pages) TI

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7−8

7.1.9

DLH[2:1]: Divisor High-Byte Registers (2 Registers)

These registers contain the high-bye of the baud-rate divisor.

D15

D14

D13

D12

D11

D10

R/W

BIT

NAME

RESET

FUNCTION

7−0

D[15:8]

00h

High-byte value of the 16-bit divisor for generation of the baud clocks in the baud rate generator.

7.1.9.1 Baud Rate Calculation

The following formulas are used to calculate the baud-rate clock and the divisors. The baud-rate clock is derived from

the 48-MHz master-clock (dividing by 6.5). Table 7−4 presents the divisors used to achieve the desired baud rates,

together with the associated rounding errors.

Baud CLK

+ 48 MHz

6.5

+ 7.384615 MHz

Divisor

+ 7.384615

106

Baud Rate

Table 7−4. DLL/DLH Values and Resulting Baud Rates

DESIRED

DLL/DLH VALUE

ACTUAL

ERROR %

DESIRED

BAUD

DEC.

HEX.

ACTUAL

BAUD

ERROR %

9 231

240F

50.00

0.002

6 154

180A

75.00

0.002

110

4 196

1064

109.99

0.005

135

3 432

0D68

134.48

0.014

150

3 077

0C05

150.00

0.002

300

1 538

0602

300.09

0.030

600

769

0301

600.18

0.030

1 200

385

0181

1 198.80

0.100

1 800

256

0100

1 802.88

0.160

2 000

231

00E7

1 998.00

0.100

2 400

192

00C0

2 403.85

0.160

3 600

128

0080

3 605.77

0.160

4 800

0060

4 807.69

0.160

7 200

0040

7 211.54

0.160

9 600

0030

9 615.38

0.160

19 200

0018

19 230.77

0.160

38 400

000C

38 461.54

0.160

57 600

0008

57 692.31

0.160

115 200

0004

115 384.62

0.160

230 400

0002

230 769.23

0.160

460 800

0001

461 538.46

0.160

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