TUSB5052 datasheet(25/82 Pages) TI

25 / 82 page

4−5

Table 4−3. Memory Mapped Registers Summary (XDATA Range = FF80−FFFF) (Continued)

ADDRESS

DESCRIPTION

FFA8

DLH1

UART1: Divisor high-byte register

FFA7

DLL1

UART1: Divisor low-byte register

FFA6

MSR1

UART1: Modem status register

FFA5

LSR1

UART1: Line status register

FFA4

MCR1

UART1: Modem control register

FFA3

FCRL1

UART1: Flow control register

FFA2

LCR1

UART1: Line control registers

FFA1

TDR1

UART1: Transmitter data registers

FFA0

RDR1

UART1: Receiver data registers

FF9E

GPIO

GPIO port data register

FF9D

GPO

GPO output data register

FF9C

GPI

GPI input data register

FF9A

GPIOCTL

GPIO port control register

↑

RESERVED

FF94

OEPINT

Output endpoint interrupt register

FF93

IEPINT

Input endpoint interrupt register

FF92

VECINT

Vector interrupt register

FF91

GLOBCTL

Global control register

FF90

ROMS

ROM shadow configuration register

↑

RESERVED

FF83

OEPBCNT_0

Output endpoint_0: Byte count register

FF82

OEPCNFG_0

Output endpoint_0: Configuration register

FF81

IEPBCNT_0

Input endpoint_0: Byte count register

FF80

IEPCNFG_0

Input endpoint_0: Configuration register

TUSB5052 Datasheet(PDF) 25 Page - Texas Instruments

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