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TUSB5052 Datasheet(PDF) 11 Page - Texas Instruments |
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TUSB5052 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 82 page  2−1 2 Main Features 2.1 General Features • Fully compliant with USB release 1.1 specifications • Supports 12-Mbps USB data rate (full speed) • Supports USB suspend and resume operations • One upstream port and five downstream ports (full and low speed) • Can support a total of 8 input endpoints and 8 output endpoints • Dual-enhanced UARTs • Integrated 8052 microcontroller with − 256 × 8 RAM for internal data − 6K × 8 ROM (with USB and I2C boot loader) − 16K × 8 RAM for code space. Totally loadable from host or I2C port. − 2K × 8 synchronous RAM used for data buffers and EDBs − Two 8052 GPIO ports, Port-1 and Port-3 − Master I2C controller for external device accesses. • Supports external microcontroller interface for development ease • Built-in four-channel DMA controller for USB/UART bulk I/O • Operates from a 6-MHz crystal. On-chip PLL generates 48/24 MHz and 7.384615 MHz for internal baud-rate generator • Power-down mode • Available in 100-pin TQFP • 3.3/5-V operation Figure 2−1 is a block diagram showing the major functional areas of the TUSB5052. 2.2 Enhanced UART Features • Software/hardware flow control − Programmable Xon/Xoff characters − Programmable auto-RTS/DTR and auto-CTS/DSR • Automatic RS485-bus transceiver control, with and without echo • Software selectable baud rate from 50 to 460,800 baud • Programmable serial-interface characteristics − 5-, 6-, 7- or 8-bit characters − Even, odd, or no parity-bit generation and detection • 1, 1.5 or 2 stop-bit generation • Line break generation and detection • Internal test and loop-back capabilities • Modem-control functions (CTS, RTS, DSR, DTR, RI, and DCD) • Internal diagnostics capability − Loopback control for communications link-fault isolation − Break, parity, overrun, framing-error simulations |
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