TUSB5052 datasheet(31/82 Pages) TI

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4−11

4.3.12 IEPSIZXY_n: Input Endpoint X/Y-Buffer Size (n = 1 to 7)

RSV

R/O

R/W

BIT

NAME

RESET

FUNCTION

6−0

S[6:0]

X and Y-buffer size:

0000.0000b Count = 0

0000.0001b Count = 1 byte

0011.1111b Count = 63 bytes

0100.0000b Count = 64 bytes

Any value

≥ 100.0001b may result in unpredictable results.

RSV

Reserved = 0

4.4

Endpoint-0 Descriptor Registers

Unlike registers EDB-1 to EDB-7, which are defined as memory entries in SRAM, endpoint_0 is described by a set

of 4 registers (two for output and two for input). The registers and their respective addresses, used for EDB-0

description, are defined in Table 4−6. EDB-0 has no Base-Address-Register, since these addresses are hardwired

into FEF8 and FEF0. Note that the bit positions have been preserved to provide consistency with EDB-n

(n = 1 to 7).

Table 4−6. Input/Output EDB-0 Registers

ADDRESS

DESCRIPTION

BASE ADDRESS

FF83

FF82

OEPBCNT_0

OEPCNFG_0

Output endpoint_0: Byte count register

Output endpoint_0: Configuration register

FEF0

FF81

FF80

IEPBCNT_0

IEPCNFG_0

Input endpoint_0: Byte count register

Input endpoint_0: Configuration register

FEF8

4.4.1

IEPCNFG_0: Input Endpoint-0 Configuration Register

UBME

RSV

TOGLE

RSV

STALL

USBIE

RSV

R/W

R/O

R/W

R/O

BIT

NAME

RESET

FUNCTION

1−0

RSV

Reserved = 0

USBIE

USB interrupt enable on transaction completion. Set/cleared by the MCU

USBIE = 0 No interrupt

USBIE = 1 Interrupt on transaction completion

STALL

USB stall condition indication. Set/cleared by the MCU

STALL

STALL = 0

STALL = 1

No stall

USB stall condition. If set by the MCU, a STALL handshake is initiated and the bit is cleared

automatically by the next setup transaction.

RSV

Reserved = 0

TOGLE

USB toggle bit. This bit reflects the toggle sequence bit of DATA0, DATA1.

RSV

Reserved = 0

UBME

UBM enable/disable bit. Set/cleared by the MCU

UBME = 0 UBM cannot use this endpoint.

UBME = 1 UBM can use this endpoint.

TUSB5052 Datasheet(PDF) 31 Page - Texas Instruments

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