LM80

SNIS102F – JUNE 1999 – REVISED MARCH 2013

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PIN DESCRIPTIONS

Pin

Pin

Number

Type

Description

Name(s)

Number

of Pins

INT_IN

1

1

Digital Input

This is an active low input that propagates the INT_IN signal to the INT

output of the LM80 via Interrupt Mask Register 1 Bit 7 and INT enable Bit

1 of the Configuration Register.

SDA

2

1

Digital I/O

Serial Bus bidirectional Data. Open-drain output.

SCL

3

1

Digital Input

Serial Bus Clock.

FAN1-FAN2

4-5

2

Digital Inputs

BTI

6

1

Digital Input

Board Temperature Interrupt driven by O.S. outputs of additional

temperature sensors such as LM75. Provides internal pull-up of 10 k

Ω.

CI (Chassis

7

1

Digital I/O

An active high input from an external circuit which latches a Chassis

Intrusion)

Intrusion event. This line can go high without any clamping action

regardless of the powered state of the LM80. The LM80 provides an

internal open drain on this line, controlled by Bit 5 of the Configuration

Register, to provide a minimum 10 ms reset of this line.

GND

8

1

GROUND

Internally connected to all of the digital circuitry.

9

1

POWER

μF

+5.75V)

(electrolytic or tantalum) and 0.1

μF (ceramic) bypass capacitors.

INT

10

1

Digital Output

Non-Maskable Interrupt (open source)/Interrupt Request (open drain).

The mode is selected with Bit 5 of the Configuration Register and the

output is enabled when Bit 1 of the Configuration Register is set to 1.

The default state is disabled.

GPO (Power Switch

11

1

Digital Output

An active low open drain output intended to drive an external P-channel

Bypass)

power MOSFET for software power control.

NTEST_IN/

12

1

Digital Input

An active-low input that enables NAND Tree board-level connectivity

RESET_IN

testing. Refer to NAND TREE TESTS on NAND Tree testing. Whenever

NAND Tree connectivity is enabled the LM80 is also reset to its power on

state.

RST_OUT/OS

13

1

Digital Output

Master Reset, 5 mA driver (open drain), active low output with a 10 ms

minimum pulse width. Available when enabled via Bit 4 in Configuration

Register and Bit 7 of the Fan Divisor/RST_OUT/OS Register. Bit 6 of the

Fan Divisor/RST_OUT/OS Register enables this output as an active low

Overtemperature Shutdown (OS).

GNDA

14

1

GROUND

Internally connected to all analog circuitry. The ground reference for all

analog inputs. This pin needs to be taken to a low noise analog ground

plane for optimum performance.

IN6-IN0

15-21

7

Analog Inputs

0V to 2.56V full scale range Analog Inputs.

A0/NTEST_OUT

22

1

Digital I/O

The lowest order bit of the Serial Bus Address. This pin functions as an

output when doing a NAND Tree test.

A1-A2

23-24

2

Digital Inputs

The two highest order bits of the Serial Bus Address.

TOTAL PINS

24

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

4

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