LM80

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SNIS102F – JUNE 1999 – REVISED MARCH 2013

Figure 7. Serial Bus Read from a Register with the Internal Address Register Preset to Desired Location

The Serial Bus control lines consists of the SDA (serial data), SCL (serial clock) and A0-A1 (address) pins. The

LM80 can only operate as a slave. The SCL line only controls the serial interface, all other clock functions within

LM80 such as the ADC and fan counters are done with a separate asynchronous internal clock.

When using the Serial Bus Interface a write will always consist of the LM80 Serial Bus Interface Address byte,

followed by the Internal Address Register byte, then the data byte. There are two cases for a read:

1. If the Internal Address Register is known to be at the desired Address, simply read the LM80 with the Serial

Bus Interface Address byte, followed by the data byte read from the LM80.

2. If the Internal Address Register value is unknown, write to the LM80 with the Serial Bus Interface Address

byte, followed by the Internal Address Register byte. Then restart the Serial Communication with a Read

consisting of the Serial Bus Interface Address byte, followed by the data byte read from the LM80.

The default power on Serial Bus address for the LM80 is: 0101(A2)(A1)(A0) binary, where A0-A2 reflect the state

of the pins defined by the same names.

All of these communications are depicted in the Serial Bus Interface Timing Diagrams as shown in Serial Bus

Timing.

USING THE LM80

Power On

When power is first applied, the LM80 performs a “power on reset” on several of its registers. The power on

condition of registers is shown in Table 1. Registers whose power on values are not shown have power on

conditions that are indeterminate (this includes the value RAM and WATCHDOG limits). The ADC is inactive. In

most applications, usually the first action after power on would be to write WATCHDOG limits into the Value

RAM.

Resets

Configuration Register INITIALIZATION accomplishes the same function as power on reset. The Value RAM

conversion results, and Value RAM WATCHDOG limits are not Reset and will be indeterminate immediately after

power on. If the Value RAM contains valid conversion results and/or Value RAM WATCHDOG limits have been

previously set, they will not be affected by a Configuration Register INITIALIZATION. Power on reset, or

Configuration Register INITIALIZATION, clear or initialize the following registers (the initialized values are shown

in Table 1):

•

Configuration Register

•

Interrupt Status Register 1

•

Interrupt Status Register 2

•

Interrupt Mask Register 1

•

Interrupt Mask Register 2

•

Fan Divisor/RST_OUT/OS Register

•

OS Configuration/Temperature Resolution Register

•

Value Ram (Registers at Address 20h - 3Fh, which include: Temperature reading, IN0-IN6 readings, FAN1

and FAN2 readings, and WATCHDOG limits)

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