LM80 datasheet(8/35 Pages) TI1

8 / 35 page

LM80

SNIS102F – JUNE 1999 – REVISED MARCH 2013

www.ti.com

AC Electrical Characteristics

The following specifications apply for +2.8 VDC ≤V

+ ≤ +3.8 V

DC for LM80CIMT-3, +4.25 VDC ≤V

+ ≤ +5.75 V

DC for LM80CIMT-5,

unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25°C.

(1)

Symbol

Typical(2)

Limits(3)

Units

Parameter

Conditions

(Limits)

SERIAL BUS TIMING CHARACTERISTICS

SCL (Clock) Period

2.5

μs (min)

Data In Setup Time to SCL High

100

ns (min)

Data Out Stable After SCL Low

ns (min)

SDA Low Setup Time to SCL Low (start)

100

ns (min)

SDA High Hold Time After SCL High (stop)

100

ns (min)

(1)

Timing specifications are tested at the Serial Bus Input logic levels, VIN(0) = 0.3 × V

+ for a falling edge and V

IN(1) =0.7 × V

+ for a rising

edge, when the SCL and SDA edge rates are similar.

(2)

Typicals are at TJ=TA=25°C and represent most likely parametric norm.

(3)

Limits are specified to AOQL (Average Outgoing Quality Level).

Figure 1. Serial Bus Timing Diagram

Figure 2. ESD Protection Input Structure

Pin Name

INT_IN

x(1)

NTEST_IN/

Reset_IN

IN0-IN6

GPO

BTI

FAN1–FAN2

INT

SCL

A1-A2

SDA

A0/NTEST_Out

RST_OUT/OS

(1)

An x indicates that the diode exists.

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