FDC37C669 datasheet(38/164 Pages) SMSC

38 / 164 page

PS/2 mode - (IDENT low, MFM high)

This mode supports the PS/2 models 50/60/80

configuration and register set. The DMA bit of

the DOR becomes a "don't care", (FINTR and

DRQ are always valid), TC and DENSEL

become active low.

Model 30 mode - (IDENT low, MFM low)

This

mode

supports

PS/2

Model

configuration and register set. The DMA enable

bit of ther DOR becomes valid (FINTR and DRQ

can be hi Z), TC is active high and DENSEL is

active low.

DMA TRANSFERS

DMA transfers are enabled with the Specify

command and are initiated by the FDC by

activating the FDRQ pin during a data transfer

command.

The FIFO is enabled directly by

asserting nDACK and addresses need not be

valid.

Note that if the DMA controller (i.e. 8237A) is

programmed to function in verify mode, a

pseudo read is performed by the FDC based

only on nDACK.

This mode is only available

when the FDC

has been configured into byte

mode (FIFO disabled) and is programmed to do

a read.

With the FIFO enabled, the FDC can

perform the above operation by using the new

Verify command; no DMA operation is needed.

CONTROLLER PHASES

For simplicity, command handling in the FDC

can be divided into three phases: Command,

Execution, and Result. Each phase is described

in the following sections.

Command Phase

After a reset, the FDC enters the command

phase and is ready to accept a command from

the host. For each of the commands, a defined

set of command code bytes and parameter

bytes has to be written to the FDC before the

command phase is complete. (Please refer to

Table 18 for the command set descriptions).

These bytes of data must be transferred in the

order prescribed.

Before writing to the FDC, the host must

examine the RQM and DIO bits of the Main

Status Register. RQM and DIO must be equal

to "1" and "0" respectively before command

bytes may be written. RQM is set false by the

FDC after each write cycle until the received

byte is processed. The FDC asserts RQM again

to request each parameter byte of the command

unless

illegal

command

condition

detected.

After the last parameter byte is

received, RQM remains "0" and the FDC

automatically enters the next phase as defined

by the command definition.

The FIFO is disabled during the command

phase to provide for the proper handling of the

"Invalid Command" condition.

Execution Phase

All data transfers to or from the FDC occur

during the execution phase, which can proceed

in DMA or non-DMA mode as indicated in the

Specify command.

After a reset, the FIFO is disabled. Each data

byte is transferred by an FINT or FDRQ

depending on the DMA mode.

The Configure

command can enable the FIFO and set the

FIFO threshold value.

The following paragraphs detail the operation of

the FIFO flow control.

In these descriptions,

<threshold> is defined as the number of bytes

available to the FDC when service is requested

from the host and ranges from 1 to 16.

The

parameter FIFOTHR, which the user programs,

is one less and ranges from 0 to 15.

FDC37C669 Datasheet(PDF) 38 Page - SMSC Corporation

FDC37C669 Datasheet(HTML) 38 Page - SMSC Corporation

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