STA400A datasheet(10/117 Pages) STMICROELECTRONICS

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STA400A

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FUNCTIONAL DESCRIPTION

The main inputs of the STA400A Channel Decoder are the 2nd IF analog signals centered at 6.095 MHz for the

satellite and at 2.99 MHz for the terrestrial branch. The final down-convertion to baseband of the three signals

is digitally performed inside the chip. After the demodulation process, the three TDM data streams are available

and stored into the external memory for further digital processing including TDM decoding and demultiplexing,

time and spatial diversity combining, FEC processing and data stream generation for the external source de-

coding.

The external memory and the PRC-based packed structure of the service layer allow the use of one Viterbi

decoder and RS decoder for the FEC processing of both the combined satellite and terrestrial frames.

The STA400A is designed to work with the STA450A Service/Source Decoder, an external RF Tuner and a

128Mbit Synchronous DRAM. Figure 3 depicts the connection block diagram of the STA400A Channel Decoder

and the external components. The 128Mbit SDRAM may be selected as a single 4Mx8Bitx4Banks or as a dual

2Mx8Bitx4Banks Memory. In the latter case the MCS0 pin must be connected to the chip select input of the

memory and the XMEM_TYPE register (address 0x0630) must be programmed with "0x01" (see section 2.8).

STA400A is fully configurable via the I2C-bus interface.

Figure 3. STA400A Connection Diagram

The 23.92 MHz system clock applied to XTI/MCLK input (pin 33) can be generated by the built-in clock buffer

and an XTAL pi-network as showed in fig.3 or may come from an external source. In both cases the quartz or

the external source must be compliant with the specifications given in the I/O Cell Description (section 3).

In fig.3 the two embedded 10 bits ADCs are used to sample and convert to digital the satellite and terrestrial IF

signals from the tuner. An internal mux, controlled by the ADCSEL input (pin 34), may be used to by-pass the

TUNER

10k

Terr ADC Diff. Input

Sat ADC Diff. Input

AGCs Control

STA400

STA450

IF2TA_N

IF2SA_P

IF2SA_N

TAGC

SAGC

ADCSEL

PCSD1

PCSD

PCDC1

PCDC

MFP_CLK

PLL_SYNC

MCLKO

CLK_IN

DATA LINE

CLK LINE

SDRAM#0

IF2TA_P

ADDRESS BUS - 12

DATA BUS - 8

BANK ADDRESS - 2

I/O MASK - 1

COMMAND INPUTS - 3

MCS0

MCS1

CHIP SELECT

SDRAM#1

TO MICROCONTROLLER

IF2TA_P

To Functional Test

Interface

XTI/MCLK

XTO

Mobile

Adapter

22pF

23.92 MHz

From

External

Source

PCFS1

PCFS

PCTS_EF1

PCTS_EF

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