TMS570LS3137 datasheet(145/173 Pages) TI1

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TMS570LS3137

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SPNS162C – APRIL 2012 – REVISED APRIL 2015

7.10.4 MibSPI/SPI Master Mode I/O Timing Specifications

Table 7-24. SPI Master Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO

= output, and SPISOMI = input)(1)(2)(3)

NO.

PARAMETER

MIN

MAX

UNIT

tc(SPC)M

Cycle time, SPICLK(4)

256tc(VCLK)

Pulse duration, SPICLK high (clock

tw(SPCH)M

0.5tc(SPC)M – tr(SPC)M – 3

0.5tc(SPC)M + 3

polarity = 0)

2(5)

Pulse duration, SPICLK low (clock

tw(SPCL)M

0.5tc(SPC)M – tf(SPC)M – 3

0.5tc(SPC)M + 3

polarity = 1)

Pulse duration, SPICLK low (clock

tw(SPCL)M

0.5tc(SPC)M – tf(SPC)M – 3

0.5tc(SPC)M + 3

polarity = 0)

3(5)

Pulse duration, SPICLK high (clock

tw(SPCH)M

0.5tc(SPC)M – tr(SPC)M – 3

0.5tc(SPC)M + 3

polarity = 1)

Delay time, SPISIMO valid before

td(SPCH-SIMO)M

0.5tc(SPC)M – 6

SPICLK low (clock polarity = 0)

4(5)

Delay time, SPISIMO valid before

td(SPCL-SIMO)M

0.5tc(SPC)M – 6

SPICLK high (clock polarity = 1)

Valid time, SPISIMO data valid after

tv(SPCL-SIMO)M

0.5tc(SPC)M – tf(SPC) – 4

SPICLK low (clock polarity = 0)

5(5)

Valid time, SPISIMO data valid after

tv(SPCH-SIMO)M

0.5tc(SPC)M – tr(SPC) – 4

SPICLK high (clock polarity = 1)

Setup time, SPISOMI before SPICLK

tsu(SOMI-SPCL)M

tf(SPC) + 2.2

low (clock polarity = 0)

6(5)

Setup time, SPISOMI before SPICLK

tsu(SOMI-SPCH)M

tr(SPC) + 2.2

high (clock polarity = 1)

Hold time, SPISOMI data valid after

th(SPCL-SOMI)M

SPICLK low (clock polarity = 0)

7(5)

Hold time, SPISOMI data valid after

th(SPCH-SOMI)M

SPICLK high (clock polarity = 1)

C2TDELAY*tc(VCLK) + 2*tc(VCLK)

(C2TDELAY+2) * tc(VCLK) -

CSHOLD = 0

Setup time CS active

- tf(SPICS) + tr(SPC) – 7

tf(SPICS) + tr(SPC) + 5.5

until SPICLK high

C2TDELAY*tc(VCLK) + 3*tc(VCLK)

(C2TDELAY+3) * tc(VCLK) -

(clock polarity = 0)

CSHOLD = 1

- tf(SPICS) + tr(SPC) – 7

tf(SPICS) + tr(SPC) + 5.5

8(6)

tC2TDELAY

C2TDELAY*tc(VCLK) + 2*tc(VCLK)

(C2TDELAY+2) * tc(VCLK) -

CSHOLD = 0

Setup time CS active

- tf(SPICS) + tf(SPC) – 7

tf(SPICS) + tf(SPC) + 5.5

until SPICLK low

C2TDELAY*tc(VCLK) + 3*tc(VCLK)

(C2TDELAY+3) * tc(VCLK) -

(clock polarity = 1)

CSHOLD = 1

- tf(SPICS) + tf(SPC) – 7

tf(SPICS) + tf(SPC) + 5.5

0.5*tc(SPC)M +

Hold time SPICLK low until CS inactive

T2CDELAY*tc(VCLK) + tc(VCLK) -

(clock polarity = 0)

tf(SPC) + tr(SPICS) - 7

tf(SPC) + tr(SPICS) + 11

9(6)

tT2CDELAY

0.5*tc(SPC)M +

Hold time SPICLK high until CS

T2CDELAY*tc(VCLK) + tc(VCLK) -

inactive (clock polarity = 1)

tr(SPC) + tr(SPICS) - 7

tr(SPC) + tr(SPICS) + 11

(C2TDELAY+1) * tc(VCLK) -

tSPIENA

SPIENAn Sample point

(C2TDELAY+1)*tc(VCLK)

tf(SPICS) – 29

SPIENAn Sample point from write to

tSPIENAW

(C2TDELAY+2)*tc(VCLK)

buffer

(1)

The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is cleared.

(2)

tc(VCLK) = interface clock cycle time = 1 / f(VCLK)

(3)

For rise and fall timings, see Table 5-7.

(4)

When the SPI is in Master mode, the following must be true:

For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(VCLK) ≥ 40ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.

For PS values of 0: tc(SPC)M = 2tc(VCLK) ≥ 40ns.

The external load on the SPICLK pin must be less than 60pF.

(5)

The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

(6)

C2TDELAY and T2CDELAY is programmed in the SPIDELAY register

Peripheral Information and Electrical Specifications

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