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TMS570LS3137 Datasheet(PDF) 147 Page - Texas Instruments

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Part # TMS570LS3137
Description  TMS570LS3137 16- and 32-Bit RISC Flash Microcontroller
PDF  173 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TMS570LS3137 Datasheet(HTML) 147 Page - Texas Instruments

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TMS570LS3137
www.ti.com
SPNS162C – APRIL 2012 – REVISED APRIL 2015
Table 7-25. SPI Master Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO
= output, and SPISOMI = input)(1)(2)(3)
NO.
PARAMETER
MIN
MAX UNIT
1
tc(SPC)M
Cycle time, SPICLK (4)
40
256tc(VCLK)
ns
Pulse duration, SPICLK high (clock
tw(SPCH)M
0.5tc(SPC)M – tr(SPC)M – 3
0.5tc(SPC)M + 3
polarity = 0)
2(5)
ns
Pulse duration, SPICLK low (clock
tw(SPCL)M
0.5tc(SPC)M – tf(SPC)M – 3
0.5tc(SPC)M + 3
polarity = 1)
Pulse duration, SPICLK low (clock
tw(SPCL)M
0.5tc(SPC)M – tf(SPC)M – 3
0.5tc(SPC)M + 3
polarity = 0)
3(5)
ns
Pulse duration, SPICLK high (clock
tw(SPCH)M
0.5tc(SPC)M – tr(SPC)M – 3
0.5tc(SPC)M + 3
polarity = 1)
Valid time, SPICLK high after
tv(SIMO-SPCH)M
SPISIMO data valid (clock polarity =
0.5tc(SPC)M – 6
0)
4(5)
ns
Valid time, SPICLK low after
tv(SIMO-SPCL)M
SPISIMO data valid (clock polarity =
0.5tc(SPC)M – 6
1)
Valid time, SPISIMO data valid after
tv(SPCH-SIMO)M
0.5tc(SPC)M – tr(SPC) – 4
SPICLK high (clock polarity = 0)
5(5)
ns
Valid time, SPISIMO data valid after
tv(SPCL-SIMO)M
0.5tc(SPC)M – tf(SPC) – 4
SPICLK low (clock polarity = 1)
Setup time, SPISOMI before
tsu(SOMI-SPCH)M
tr(SPC) + 2.2
SPICLK high (clock polarity = 0)
6(5)
ns
Setup time, SPISOMI before
tsu(SOMI-SPCL)M
tf(SPC) + 2.2
SPICLK low (clock polarity = 1)
Valid time, SPISOMI data valid after
tv(SPCH-SOMI)M
10
SPICLK high (clock polarity = 0)
7(5)
ns
Valid time, SPISOMI data valid after
tv(SPCL-SOMI)M
10
SPICLK low (clock polarity = 1)
0.5*tc(SPC)M +
0.5*tc(SPC)M +
CSHOLD = 0
(C2TDELAY+2) * tc(VCLK) -
(C2TDELAY+2) * tc(VCLK) -
Setup time CS
tf(SPICS) + tr(SPC) – 7
tf(SPICS) + tr(SPC) + 5.5
active until SPICLK
high (clock polarity =
0.5*tc(SPC)M +
0.5*tc(SPC)M +
0)
CSHOLD = 1
(C2TDELAY+3) * tc(VCLK) -
(C2TDELAY+3) * tc(VCLK) -
tf(SPICS) + tr(SPC) – 7
tf(SPICS) + tr(SPC) + 5.5
8(6)
tC2TDELAY
ns
0.5*tc(SPC)M +
0.5*tc(SPC)M +
CSHOLD = 0
(C2TDELAY+2) * tc(VCLK) -
(C2TDELAY+2) * tc(VCLK) -
Setup time CS
tf(SPICS) + tf(SPC) – 7
tf(SPICS) + tf(SPC) + 5.5
active until SPICLK
low (clock polarity =
0.5*tc(SPC)M +
0.5*tc(SPC)M +
1)
CSHOLD = 1
(C2TDELAY+3) * tc(VCLK) -
(C2TDELAY+3) * tc(VCLK) -
tf(SPICS) + tf(SPC) – 7
tf(SPICS) + tf(SPC) + 5.5
T2CDELAY*tc(VCLK) +
T2CDELAY*tc(VCLK) +
Hold time SPICLK low until CS
tc(VCLK) - tf(SPC) + tr(SPICS) -
tc(VCLK) - tf(SPC) + tr(SPICS) +
inactive (clock polarity = 0)
7
11
9(6)
tT2CDELAY
ns
T2CDELAY*tc(VCLK) +
T2CDELAY*tc(VCLK) +
Hold time SPICLK high until CS
tc(VCLK) - tr(SPC) + tr(SPICS) -
tc(VCLK) - tr(SPC) + tr(SPICS) +
inactive (clock polarity = 1)
7
11
(C2TDELAY+1)* tc(VCLK) -
ns
10
tSPIENA
SPIENAn Sample Point
(C2TDELAY+1)*tc(VCLK)
tf(SPICS) – 29
SPIENAn Sample point from write to
ns
11
tSPIENAW
(C2TDELAY+2)*tc(VCLK)
buffer
(1)
The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set.
(2)
tc(VCLK) = interface clock cycle time = 1 / f(VCLK)
(3)
For rise and fall timings, see the Table 5-7.
(4)
When the SPI is in Master mode, the following must be true:
For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(VCLK) ≥ 40ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: tc(SPC)M = 2tc(VCLK) ≥ 40ns.
The external load on the SPICLK pin must be less than 60pF.
(5)
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
(6)
C2TDELAY and T2CDELAY is programmed in the SPIDELAY register
Copyright © 2012–2015, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
147
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