Silan

Semiconductors

SC9256

HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD

REV: 1.0

2002.01.30.

19

"H" level

High impedance

"L" level

Reference frequency

Programmable

counter output

DO output

Phase comparator

Lock detection strobe

Unlock is reset (RESET)

Unlock F/F (UNLOCK)

Lock enable (ENABLE)

Phase error detection

Counts phase difference.

Fig.10

LSB

MSB

Address D2H

LSB

MSB

Address D3H

Input register

Output register

ENA-

BLE

UN

LOCK

RESET

Setting data to "1" resets unlock detection bit and lock enable bit.

1

0

PLL lock detection enabled

PLL lock detection in waiting

state

1

0

PLLinunlocked state(*)

PLLinlocked state

Note: The asterisk (*) indicates an error state of over 180

° phase difference relative to the reference frequency

2. Phase error detection bits (PE1~PE3)

The unlock bit detects, using the reference frequency cycle, the phase difference between the reference

frequency and the divided output of the programmable counter. The phase error detection bits (bits PE1~PE3)

are capable of precise phase error detection of

±0.55µs~±7.15µs using the reference frequency cycle.( If the

UNLOCK bit is set to “1” and the phase difference relative to the reference frequency is over 180

°,bits

PE1~PE3 cannot correctly detect the phase error. Therefore, bits PE1~PE3 are normally used when the

UNLOCK bit is set to “0”.) Bits PE1~PE3 detect phase error normally when the phase difference is -180

°~180°

relative to the reference frequency cycle.