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SC9256 Datasheet(PDF) 6 Page - Silan Microelectronics Joint-stock

Part # SC9256
Description  PLL FOR DTS
PDF  24 Pages
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Manufacturer  SILAN [Silan Microelectronics Joint-stock]
Direct Link  http://www.silan.com.cn
Logo SILAN - Silan Microelectronics Joint-stock

SC9256 Datasheet(HTML) 6 Page - Silan Microelectronics Joint-stock

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Silan
Semiconductors
SC9256
HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD
REV: 1.0
2002.01.30.
6
FUNCTION DESCRIPTION
Serial I/O ports
As the block diagram shows, the functions are controlled by setting data in the 48 bits contained in each of the 2
sets
of 24 bit registers. Each bit of data in these register is transferred through the serial ports between the
controller and the DATA, CLOCK and PERIOD pins. Each serial transfer consists of a total of 32 bits, with 8
address bits and 24 data bits.
Since all functions are controlled in units of registers, the explanation in this manual focuses on the 8 bit address
and functions of each register.
These registers consist of 24 bits and are selected by an 8 bit address.
A list of the address assignment for each register is given below under register assignments.
Register
Address
Contents of 24 bits
No. of bit
Input
register 1
D0H
PLL divisor setting
Reference frequency setting
PLL input and mode setting
Crystal oscillator selection
16
4
2
2
total 24
Input
register 2
D2H
General=purpose counter control (including lock detection bit
control)
I/O port and general-purpose counter switching bits
I/O-5/CLK pin switching bit
DO pin control
Test bit
I/O port control (also used as general-purpose counter input
selection bits)
Output data
4
3
1
1
1
5
9
total 24
Output
register 1
D1H
General-purpose counter numeric data
Not used
22
2
total 24
Output
register 2
D3H
Lock detection data
I/O port control data
Output data
Input data (undefined during output port selection)
Not used
5
5
4
5
5
total 24
When the PERIOD signal falls, the input data are latched in register 1 or register 2 and the function is performed.
When the CLOCK signal falls for 9 time, the output data are latched in parallel in the output registers. The data
are subsequently output serially from the data pin.



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