TPS650941 datasheet(39/92 Pages) TI1

39 / 92 page

TPS65094, TPS650940, TPS650941, TPS650942, TPS650944

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SWCS133A – SEPTEMBER 2015 – REVISED JUNE 2016

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Detailed Description

6.4.4.3

Load Switches

The PMIC features three general-purpose load switches. SWA1 has a power input pin (PVINSWA1), while

SWB1 and SWB2 share a power input pin (PVINSWB1_B2). All switches have built-in slew rate control

during start-up to limit the inrush current.

Table 6-7 lists the control signals for enabling and disabling each LDO and load switch.

(1)

For LPDDR3 and LPDDR4 memory, SWB1_2 is configured to

V1P8U and controlled by SLP_S4B. For DDR3L memory, SWB1_2

is configured to either V3P3S or V1P8S and controlled by SLP_S3B.

(2)

When LDOLS_EN = 0, the user can write to enable bits in Reg

0xA0–Reg 0xA1 to enable or disable the rails. Alternatively, all of

them could be factory configured to be part of sequence along with

other voltage rails. Pin name changed to SWA1_EN when LDOA1 is

factory programmed to always on.

(3)

When SWA1_EN = 0, the user can write to enable bits in Reg

0xA0–Reg 0xA1 to enable or disable the rails. Alternatively, all of

them could be factory configured to be part of sequence along with

other voltage rails. Pin name changed to LDOLS_EN when LDOA1

is not factory programmed to always on.

(4)

BUCK6_PG should be asserted as well.

Table 6-7. Summary of LDO and Load Switch Control

CONTROL SIGNAL

RAIL

SLP_S4B or SLP_S3B(1)

SWB1_2

LDOLS_EN(2)

LDOA2, LDOA3, SWA1

SWA1_EN(3)

SWA1

SLP_S0B(4)

VTT LDO

TPS650941 Datasheet(PDF) 39 Page - Texas Instruments