TPS650941 datasheet(63/92 Pages) TI1

63 / 92 page

TPS65094, TPS650940, TPS650941, TPS650942, TPS650944

www.ti.com

SWCS133A – SEPTEMBER 2015 – REVISED JUNE 2016

Submit Documentation Feedback

Product Folder Links: TPS65094

Detailed Description

Table 6-35. VR_CTRL2 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

BUCK5_EN

R/W

BUCK5 Enable bit.

0: BUCK5 operates normally.

1: Enabled regardless of power sequencing

BUCK4_EN

R/W

BUCK4 Enable bit.

0: BUCK4 operates normally.

1: Enabled regardless of power sequencing

BUCK3_EN

R/W

BUCK3 Enable bit. BUCK3_DISABLEB has priority over BUCK3_EN.

0: BUCK3 operates normally.

1: Enabled regardless of power sequencing, unless BUCK3_DISABLEB = 0

BUCK2_EN

R/W

BUCK2 Enable bit. BUCK2_DISABLEB has priority over BUCK2_EN.

0: BUCK2 operates normally.

1: Enabled regardless of power sequencing, unless BUCK2_DISABLEB = 0

BUCK1_EN

R/W

BUCK1 Enable bit. BUCK1_DISABLEB has priority over BUCK1_EN.

0: BUCK1 operates normally.

1: Enabled regardless of power sequencing, unless BUCK1_DISABLEB = 0

6.7.25 VR_CTRL3: VR Enable/Disable Register (offset = 9Fh) [reset = 0111 0000]

Figure 6-43. VR_CTRL3 Register (Offset = 9Fh) [reset = 0111 0000]

Bit

Bit Name

RESERVED

SWB1_2_

DISABLEB

SWA1_

DISABLEB

VTT_

DISABLEB

VTT_EN

RESERVED

SWB1_2_EN

LDOA3_EN

TPS650940 and

TPS650944

TPS650941 and

TPS650942

Access

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

TPS650941 Datasheet(PDF) 63 Page - Texas Instruments

TPS650941 Datasheet(HTML) 63 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

Datasheet Download

Link URL