TPS650941 datasheet(9/92 Pages) TI1

9 / 92 page

TPS65094, TPS650940, TPS650941, TPS650942, TPS650944

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SWCS133A – SEPTEMBER 2015 – REVISED JUNE 2016

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Pin Configuration and Functions

Table 4-1. Pin Functions (continued)

NO.

NAME

I/O

SUPPLY, OP

VOLTAGE

LEVEL

DESCRIPTION

INTERFACE

PMICEN

PMIC cold-boot pin. At assertion rising edge of the signal of this pin

power state transitions from G3 to S4/S5. Driving the pin to L shuts

down all VRs.

LDOLS_EN or

SWA1_EN

Enable pin for LDOA2, LDOA3, and SWA1 when OTP is configured to

LDOLS_EN. Enable pin for just SWA1 when OTP is configured to

SWA1_EN. Resources turn on at assertion (H) and turn off at

deassertion (L) of the pin. Optionally, when the pin is pulled low, the

host can write to enable bits in Reg 0xA0–Reg 0xA1 to control the

rails.

IRQB

Open-drain output interrupt pin. Refer to Section 6.7.3, IRQ: PMIC

Interrupt Register, for definitions.

RSMRSTB

Open-drain output Always-ON-rail Power Good. It reflects a valid state

whenever VSYS is available.

GPO

Open-drain output controlled by an I2C register bit defined in

Section 6.7.26, GPO_CTRL: GPO Control Register, by the user,

which then can be used as an enable signal to an external VR.

PCH_PWROK

Open-drain output global Power Good. It reflects a valid state

whenever VSYS is available.

PROCHOT

Optional open-drain output for indicating PMIC thermal event. Invert

before connecting to SoC if used, otherwise leave floating.

CLK

I2C clock

DATA

I/O

I2C data

THERMTRIPB

Thermal shutdown signal from SoC

SLP_S0B

Power state pin. PMIC goes into Connected Standby at falling edge

and exits from Connected Standby at rising edge.

SLP_S3B

Power state pin. PMIC goes into S3 at falling edge and exits from S3,

transitions into S0 at rising edge.

SLP_S4B

Power state pin. PMIC goes into S4 at falling edge and exits from S4,

transitions into S3 at rising edge.

REFERENCE

VREF

1.25 V

Band-gap reference output. Stabilize it by connecting a 100-nF

(typical) ceramic capacitor between this pin and quiet ground.

AGND

—

Analog ground. Do not connect to the thermal pad ground on top

layer. Connect to ground of VREF capacitor.

VSYS

System voltage detection and input to internal LDOs (3.3 V and 5 V).

Bypass to ground with a 1-µF (typical) ceramic capacitor.

THERMAL PAD

—

Thermal pad

—

Connect to PCB ground plane using multiple vias for good thermal

and electrical performance.

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