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TPS650941 Datasheet(PDF) 14 Page - Texas Instruments

Part # TPS650941
Description  PMIC for Intel Apollo Lake Platform
PDF  92 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TPS650941 Datasheet(HTML) 14 Page - Texas Instruments

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TPS65094, TPS650940, TPS650941, TPS650942, TPS650944
SWCS133A – SEPTEMBER 2015 – REVISED JUNE 2016
www.ti.com
Submit Documentation Feedback
Product Folder Links: TPS65094
Specifications
Copyright © 2015–2016, Texas Instruments Incorporated
Electrical Characteristics: Buck Controllers (continued)
over recommended input voltage range, TA = –40°C to +85°C and TA = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
(2)
Additional overshoot of up to 100 mV is allowed as long as it lasts less than 50 µs.
RDSON_DRVH
Driver DRVH resistance
Source, IDRVH = –50 mA
3
Ω
Sink, IDRVH = 50 mA
2
RDSON_DRVL
Driver DRVL resistance
Source, IDRVL = –50 mA
3
Ω
Sink, IDRVL = 50 mA
0.4
RDIS
Output auto-discharge
resistance
BUCK1_DIS[1:0] = 01
100
Ω
BUCK1_DIS[1:0] = 10
200
BUCK1_DIS[1:0] = 11
500
CBOOT
Bootstrap capacitance
100
nF
RON_BOOT
Bootstrap switch ON
resistance
20
Ω
BUCK2
VIN
Power input voltage for
external HSD FET
5.6
13
21
V
VOUT
DC output voltage
Step size
10
mV
BUCK2_VID[6:0] = 0000000 (default)
0
V
BUCK2_VID[6:0] = 0000001
0.5
BUCK2_VID[6:0] = 0000010
0.51
⋮
⋮
BUCK2_VID[6:0] = 1110101
1.66
BUCK2_VID[6:0] = 1110110–1111111
1.67
DC output voltage
accuracy
VOUT ≥ 1 V, IOUT = 100 mA to 21 A
–2%
2%
VOUT = 0.75 V, IOUT = 100 mA to 6.3 A
–2.5%
2.5%
VOUT ≤ 0.6 V, IOUT = 10 mA
–3.5%
3.5%
Total output voltage
accuracy (DC + ripple) in
DCM
IOUT = 10 mA, VOUT ≤ 0.765 V
–20
40
mV
SR(VOUT)
Output DVS slew rate
2.5
3.125
mV/µs
ILIM_LSD
Low-side output valley
current limit accuracy
(programmed by external
resistor RLIM)
See Section 6.4.3.4, Current Limit, for details.
–15%
15%
VTH_ZC
Low-side current zero
crossing detection
threshold
–11
11
mV
ILIMREF
Source current out of
ILIM2 pin
T = 25°C
45
50
55
µA
VLIM
Voltage at ILIM2 pin
VLIM = RLIM × ILIMREF
0.2
2.25
V
ΔVOUT/ΔVIN
Line regulation
VOUT ≥ 1 V, IOUT = 21 A
–0.5%
0.5%
ΔVOUT/ΔIOUT
Load regulation
VIN = 13 V, 1 V ≤ VOUT ≤ 1.3 V,
IOUT = 0 A to 21 A,
referenced to VOUT at IOUT = 21 A
0%
1%
ΔVOUT_TR
(1)
Load transient regulation
DC + AC at sense point, VIN = 13 V, VOUT = 1 V,
IOUT = 1 A to 21 A and 21 A to 1 A with 1 µs of tr
and tf
–160
30(2)
mV
DC + AC at sense point, VIN = 13 V,
VOUT = 0.75 V, IOUT = 1 A to 3.3 A and 3.3 A to
1 A with 1 µs of tr and tf
–50
50(2)
VTH_PG
Power Good deassertion
threshold in percentage
of target VOUT
VOUT rising
108%
VOUT falling
92%



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