DS3134 datasheet(158/203 Pages) DALLAS

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DS3134

158 of 203

COMMAND BITS

Bit 0 / I/O Space Control (IOC). This read only bit is forced to zero by the device to indicate that it

does not respond to I/O Space accesses.

Bit 1 / Memory Space Control (MSC). This read/write bit controls whether or not the device will

respond to accesses by the PCI bus to the memory space (which is the Local Bus). When this bit is set to

zero, the device will ignore accesses attempted to the Local Bus and when set to one; the device will

allow accesses to the Local Bus. This bit should be set to zero when the Local Bus is operated in the

Configuration Mode. This bit is force to zero when a hardware reset is initiated via the PRST* pin.

0 = ignore accesses to the Local Bus

1 = allow accesses to the Bus

Bit 2 / Master Control (MASC). This read only bit is forced to zero by the device since it cannot act as

a bus master.

Bit 3 / Special Cycle Control (SCC). This read only bit is forced to zero by the device to indicate that it

cannot decode Special Cycle operations.

Bit 4 / Memory Write & Invalidate Command Enable (MWEN). This read only bit is forced to zero

by the device to indicate that it cannot generate the Memory Write and Invalidate command.

Bit 5 / VGA Control (VGA). This read only bit is forced to zero by the device to indicate that it is not a

VGA compatible device.

Bit 6 / Parity Error Response Control (PARC). This read/write bit controls whether or not the device

should ignore parity errors. When this bit is set to zero, the device will ignore any parity errors that it

detects and continue to operate normally. When this bit is set to one, the device must act on parity errors.

This bit is forced to zero when a hardware reset is initiated via the PRST* pin.

0 = ignore parity errors

1 = act on parity errors

Bit 7 / Address Stepping Control (STEPC). This read only bit is forced to zero by the device to indicate

that it is not capable of address/data stepping.

Bit 8 / PCI System Error Control (PSEC). This read/write bit controls whether or not the device

should enable the PSERR* output pin. When this bit is set to zero, the device will disable the PSERR*

pin and when this bit is set to one, the device will enable the PSERR* pin. This bit is forced to zero when

a hardware reset is initiated via the PRST* pin.

0 = disable the PSERR* pin

1 = enable the PSERR* pin

Bit 9 / Fast Back-to-Back Master Enable (FBBEN). This read only bit is forced to zero by the device

to indicate that it is not capable of generating fast back-to-back transactions to different agents.

Bits 10 to 15 / Reserved. These read only bits are forced to zero by the device.

DS3134 Datasheet(PDF) 158 Page - Dallas Semiconductor