DS3134 datasheet(159/203 Pages) DALLAS

159 / 203 page

DS3134

159 of 203

STATUS BITS

The upper word in the PCMD1 register is the Status portion, which report events as they occur. As

mentioned earlier, reads of the Status portion occur normally but writes are unique in that bits can only be

reset (i.e. forced to zero). This occurs when a one is written to a bit position. Writes with a zero to a bit

position have no affect. This allows individual bits to be reset.

Bits 16 to 20 / Reserved. These read only bits are forced to zero by the device.

Bit 21 / 66 MHz Capable (66 MHz). This read only bit is forced to zero by the device to indicate that it

is not capable of running at 66 MHz.

Bit 22 / User Definable Features Capable (UDF). This read only bit is forced to zero by the device to

indicate that it does not support User Definable Features.

Bit 23 / Fast Back-to-Back Capable Target (FBBCT). This read only bit is forced to one by the device

to indicate that it is capable of accepting fast back-to-back transactions when the transactions are not from

the same agent.

Bit 24 / PCI Parity Error Reported (PARR). This read only bit is forced to a zero by the device since

the device cannot act as a bus master.

Bit 25 & 26 / Device Timing Select Bits 0 & 1 (DTS0 & DTS1). These two read only bits are forced to

01b by the device to indicate that it is capable of the medium timing requirements for the PDEVSEL*

signal.

Bit 27 / Target Abort Initiated (TABT). This read/write bit will be set to a one when the device

terminates a bus transaction with a target abort. This will only occur when the Local Bus is being

operated in the bus arbitration mode and the Local Bus does not have bus control when the Host requests

access. This bit can be reset (set to zero) by the Host by writing a one to this bit.

Bit 28 / Target Abort Detected by Master (TABTM). This read only bit is forced to a zero by the

device since the device cannot act as a bus master.

Bit 29 / Master Abort (MABT). This read only bit is forced to a zero by the device since the device

cannot act as a bus master.

Bit 30 / PCI System Error Reported (PSE). This read/write bit will be set to a one when the device

asserts the PSERR* signal (even if it is disabled via the PSEC Command bit). This bit can be reset (set to

zero) by the Host by writing a one to this bit.

Bit 31 / PCI Parity Error Reported (PPE). This read/write bit will be set to a one when the device

detects a parity error (even if parity is disabled via the PARC Command bit). This bit can be reset (set to

zero) by the Host by writing a one to this bit.

DS3134 Datasheet(PDF) 159 Page - Dallas Semiconductor