MAX1021 datasheet(16/47 Pages) MAXIM

16 / 47 page

10-Bit, Multichannel ADCs/DACs with FIFO,

Temperature Sensing, and GPIO Ports

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Pin Description

MAX1020/

MAX1021

MAX1022/

MAX1023

MAX1057/

MAX1058

NAME

FUNCTION

1, 2

—

GPIOA0, GPIOA1

General-Purpose I/O A0, A1. GPIOA0, A1 can sink and source 15mA.

EOC

Active-Low End-of-Conversion Output. Data is valid after the falling edge

of EOC.

DVDD

Digital Positive-Power Input. Bypass DVDD to DGND with a 0.1µF

capacitor.

DGND

Digital Ground. Connect DGND to AGND.

DOUT

Serial-Data Output. Data is clocked out on the falling edge of the SCLK

clock in modes 00, 01, and 10. Data is clocked out on the rising edge of

the SCLK clock in mode 11. It is high impedance when CS is high.

SCLK

Serial-Clock Input. Clocks data in and out of the serial interface. (Duty

cycle must be 40% to 60%.) See Table 5 for details on programming the

clock mode.

DIN

Serial-Data Input. DIN data is latched into the serial interface on the

falling edge of SCLK.

9–12,

16–19

9–12,

16–19

12–15,

22–25

OUT0–OUT7

DAC Outputs

AVDD

Positive Analog Power Input. Bypass AVDD to AGND with a 0.1µF

capacitor.

AGND

Analog Ground

15, 23, 32,

2, 15, 24, 32

—

N.C.

No Connection. Not internally connected.

LDAC

Active-Low Load DAC. LDAC is an asynchronous active-low input that

updates the DAC outputs. Drive LDAC low to make the DAC registers

transparent.

Active-Low Chip-Select Input. When CS is low, the serial interface is

enabled. When CS is high, DOUT is high impedance.

RES_SEL

Reset Select. Select DAC wake-up mode. Set RES_SEL low to wake up

the DAC outputs with a 100k

Ω resistor to GND or set RES_SEL high to

wake up the DAC outputs with a 100k

Ω resistor to VREF. Set RES_SEL

high to power up the DAC input register to FFFh. Set RES_SEL low to

power up the DAC input register to 000h.

24, 25

—

GPIOC0, GPIOC1

General-Purpose I/O C0, C1. GPIOC0, C1 can sink 4mA and source 2mA.

MAX1021 Datasheet(PDF) 16 Page - Maxim Integrated Products

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