MAX1021 datasheet(35/47 Pages) MAXIM

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10-Bit, Multichannel ADCs/DACs with FIFO,

Temperature Sensing, and GPIO Ports

______________________________________________________________________________________

Do not issue a second CNVST signal before EOC goes

low; otherwise, the FIFO can be corrupted. Wait until all

conversions are complete before reading the FIFO. SPI

communications to the DAC and GPIO registers are per-

mitted during conversion. However, coupled noise may

result in degraded ADC signal-to-noise ratio (SNR).

Externally Timed Acquisitions and

Internally Timed Conversions with CNVST

ADC Conversions in Clock Mode 01

In clock mode 01, conversions are requested one at a

time using CNVST and performed automatically using

the internal oscillator. See Figure 7 for clock mode 01

timing after a command byte is issued.

Setting CNVST low begins an acquisition, wakes up the

ADC, and places it in track mode. Hold CNVST low for

at least 1.4µs to complete the acquisition. If reference

mode 00 or 10 is selected, an additional 45µs is

required for the internal reference to power up. If a tem-

perature measurement is being requested, reference

power-up and temperature measurement is internally

timed. In this case, hold CNVST low for at least 40µs.

Set CNVST high to begin a conversion. Sampling is

completed approximately 500ns after CNVST goes

high. After the conversion is complete, the ADC shuts

down and pulls EOC low. EOC stays low until CS or

CNVST is pulled low again. Wait until EOC goes low

before pulling CS or CNVST low. The number of CNVST

signals must equal the number of conversions request-

ed by the scan and averaging registers to correctly

update the FIFO. Wait until all conversions are com-

plete before reading the FIFO. SPI communications to

the DAC and GPIO registers are permitted during con-

(UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS)

DOUT

MSB1

tRDS

LSB1

MSB2

SCLK

CNVST

EOC

Figure 6. Clock Mode 00—After writing a command byte, set CNVST low for at least 40ns to begin a conversion.

(CONVERSION 2)

tCSW

tDOV

(ACQUISITION 2)

(ACQUISITION 1)

(CONVERSION 1)

DOUT

MSB1

LSB1

MSB2

SCLK

CNVST

EOC

Figure 7. Clock Mode 01—After writing a command byte, request multiple conversions by setting CNVST low for each conversion.

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