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MAX1021 Datasheet(PDF) 38 Page - Maxim Integrated Products |
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MAX1021 Datasheet(HTML) 38 Page - Maxim Integrated Products |
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38 / 47 page ![]() 10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports 38 ______________________________________________________________________________________ tCSH SCLK DIN DOUT CS 12 3 4 32 16 8 D15 D14 D13 D12 D11 5 D15 D7 D14 D6 D13 D5 D12 D4 D0 D1 D0 tDOD tDOT tCSS tCSPWH D1 tDOE tDS tDH tCH tCL Figure 10. DAC/GPIO Serial-Interface Timing (Clock Modes 00, 01, and 10) DAC/GPIO Timing Figures 10–13 detail the timing diagrams for writing to the DAC and GPIOs. Figure 10 shows the timing speci- fications for clock modes 00, 01, and 10. Figure 11 shows the timing specifications for clock mode 11. Figure 12 details the timing specifications for the DAC input select register and 2 bytes to follow. Output data is updated on the rising edge of SCLK in clock mode 11. Figure 13 shows the GPIO timing. Figure 14 shows the timing details of a hardware LDAC command DAC- register update. For a software-command DAC-register update, tS is valid from the rising edge of CS, which fol- lows the last data bit in the software command word. |
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