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ML7066 Datasheet(PDF) 15 Page - LAPIS Semiconductor Co., Ltd. |
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ML7066 Datasheet(HTML) 15 Page - LAPIS Semiconductor Co., Ltd. |
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15 / 29 page ![]() FEDL7066-01 ML7066 15/29 Recommneded Operation Conditions Item Symbol Condition Min. Typ. Max. Unit Power supply voltage (I/O) VDDIO VDDIO pin (*3) 2.1 3.0 3.6 V Power supply voltage (RF) VDD_RF (*2) (*4) RX 1.95 2.1 2.3 V (*2) (*4) TX 1.92 2.1 2.3 V Regulator input voltage VREGIN VREG_IN Pin (*3) 2.1 3.0 3.6 V Operating temperature Ta — -25 +25 +65 ℃ Digital input rise time TIR Digital input pins (*5) — — 20 ns Digital input fall time tIF Digital input pins (*5) — — 20 ns Digital output load CDL All digital output pins — — 20 pF Master clock FMCK XI pin (*20) -4ppm 19.2 +4ppm MHz Master clock duty ratio DMCK XI pin 45 50 55 % Sub clock FEXTCLK EXTCLK pin (*21) -80ppm 32.768 +80ppm kHz Sub clock duty ratio DEXTCLK EXTCLK pin 40 50 60 % SCI clock input frequency FSCLK SCLK pin 0.1 2 8 MHz SCI clock input duty ratio DSCLK SCLK pin 45 50 55 % RF channel frequency1 FRF1 RF_OUT pin, RF_IN pin 12.5kHz interval 426.0250 — 426.8375 MHz RF channel frequency2 FRF2 RF_OUT pin, RF_IN pin 12.5kHz interval 429.1750 — 429.9250 MHz *3: VDDIO=VREGIN *4: The VREG_OUT pin should be connected to each RF power supply pin. *5: Applies to the pins that are indicated as I, IS, IU in the I/O column in the Pin Descriptions section. *20: The input clock frequency deviation is shown in the following table. *21: Reference value. The frequency accuracy of the sub clock only affects timers, and does not matter for the transmit/receive operation. Table:Example of Input Clock Frequency and Receive Characteristics Reference clock frequency accuracy 21.4MHz quartz filter (BPF) characteristics 455kHz ceramic filter (BPF) characteristics ±4ppm ±10ppm ±20ppm ±40ppm ±60ppm ±6kHz ±6kHz ±6kHz ±6kHz ±6kHz ±6.0kHz ±7.5kHz ±7.5kHz ±7.5kHz ±7.5kHz You can use the PLL frequency adjustment function provided in this LSI to support a reference clock frequency with an accuracy worse than ±4ppm. When the accuracy of the reference clock frequency is worse than ±4ppm, you can adjust it to ensure the required frequency accuracy by the PLL frequency adjustment function. In terms of the receive characteristics, the bandwidth of the external filter should be wide as shown in this table if the accuracy of the source reference clock frequency is worse than ±4ppm, which degrades the C/I characteristics. In this table, the reference clock frequency accuracy includes the center frequency and the temperature variation. The temperature variation of the reference clock frequency is uniformly assumed to be ±20ppm. |
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