FEDL7066-01

ML7066

17/29

DC Common Characteristics

Item

Symbol

Condition

Min.

Typ.

Max.

Unit

(*9)(*10)(*11) XI pin excluded

—

V

"H" level input voltage

XI pin

X 0.9

—

V

(*9)(*10)(*11) XI pin excluded

0

—

V

"L" level input voltage

XI pin

0

—

X 0.25

V

Schmitt trigger "H" level

judgment threshold

(*10)

—

1.2

1.8

V

Schmitt trigger "L" level

judgment threshold

(*10)

0.4

0.8

—

V

(*9)(*10)(*11)

-2

—

2

µA

(*19)

-2

—

2.3

µA

VIL=0V

(*9)(*10)

-2

—

2

µA

VIL=0V

(*11)

-200

-25

-5

µA

Input leakage current

VIL=0V

(*19)

-2.3

—

2

µA

IOH=-100µA

(*13)

—

V

—

V

—

V

"H" level output voltage

IOH=-100µA

(*18)

1.65

—

2.35

V

IOL=100µA

(*13)

0

—

0.2

V

IOL=4mA

(*13)

0

—

V

"L" level output voltage

IOH=-100µA

(*18)

0

—

0.45

V

When VREG_CORE pin is sleeping

1.2

1.7

2.2

V

When VREG_CORE pin is idling,

transmitting, and receiving

1.95

2.2

2.3

V

Regulator output

voltage

When VREG_OUT pin is

transmitting and receiving

1.95

2.2

2.3

V

Input pin

(*9)(*10)(*11)

—

6

—

pF

Output pin

(*13)

—

9

—

pF

RF input pin

(*14)

—

9

—

pF

RF output pin

(*15)

—

9

—

pF

Analog input pin

(*16)

—

9

—

pF

Input capacitance

Analog output pin

(*17)

—

9

—

pF

(*9) Applies to the pins indicated as I in the I/O column in the Pin Descriptions section.

*13: Applies to the pins that are indicated as O in the I/O column in the Pin Descriptions section, except for the XO pin.