CS8420 datasheet(64/80 Pages) CIRRUS

64 / 80 page

CS8420

DS245PP2

14.6

Hardware Mode 5 Description

(AES3 Receiver Only)

Hardware Mode 5 data flow is shown in Figure 30.

Audio data is input via the AES3 receiver, and rout-

ed to the serial audio output port. The PRO, COPY,

ORIG, EMPH, and AUDIO channel status bits are

output on pins. The decoded C and U bits are also

output, clocked by both edges of OLRCK (master

mode only, see Figure 21).

If a validity, parity, bi-phase or lock receiver error

occurs, the current audio sample is passed unmod-

ified to the serial audio output port.

Start-up options are shown in Table 12, and allow

choice of the serial audio output port as a master or

slave, and the serial audio port format. The follow-

ing pages contain the detailed pin descriptions for

hardware mode 5.

Serial

Audio

Output

AES3 Rx

Decoder

C& Ubit Data Buffer

RXP

RXN

OLRCK

OSCLK

SDOUT

RMCK

RERR

COPY ORIG

EMPH

RCBL

PRO AUDIO

CHS

DFC0

DFC1

S/AES

VD+

H/S

Power supply pins (VD+, VA+, DGND, AGND) & the reset pin (RST) and the PLL filter pin (FILT)

are omitted from this diagram. Please refer to the Typical Connection Diagram for hook-up details.

VD+

NVERR

OMCK

Figure 30. Hardware Mode 5 - AES3 Receiver Only

SDOUT ORIG EMPH

Function

Serial Output Port is Slave

Serial Output Port is Master

Serial Output Format OF1

Serial Output Format OF2

Serial Output Format OF3

Serial Output Format OF5

Table 12. Hardware Mode 5 Start-up Options

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