CS8420 datasheet(68/80 Pages) CIRRUS

68 / 80 page

CS8420

DS245PP2

14.7.1

Pin Description - Hardware Mode 6

Overall Device Control:

DFC0, DFC1 - Data Flow Control Inputs

DFC0 and DFC1 inputs determine the major data flow options available in hardware mode, according to

Table 3.

S/AES - Serial Audio or AES3 Input Select

S/AES is connected to VD+ in hardware mode 6, in order to select the serial audio input.

SFMT0, SFMT1 - Serial Audio Input Port Data Format Select Inputs

SFMT0 and SFMT1 select the serial audio input port format. See Table 14.

OMCK - Output Section Master Clock Input

Output section master clock input. The frequency must be 256x the output sample rate (Fso).

Audio Input Interface:

SDIN - Serial Audio Input Port Data Input

Audio data serial input pin.

ISCLK - Serial Audio Input Port Bit Clock Input or Output

Serial bit clock for audio data on the SDIN pin.

ILRCK - Serial Audio Input Port Left/Right Clock Input or Output

Word rate clock for the audio data on the SDIN pin.

APMS - Serial Audio Input Port Master or Slave

APMS should be connected to VD+ to set serial audio input port as a master, or connected to DGND to

set the port as a slave.

AES3/SPDIF Transmitter Interface:

TXN, TXP - Differential Line Driver Outputs

Differential line driver outputs, transmitting AES3 type data. Drivers are pulled to low while the CS8420

is in the reset state.

* Pins which remain the same function in all modes.

COPY/C

DFC0

EMPH

SFMT0

SFMT1

VA+

AGND

FILT

RST

APMS

TCBLD

ILRCK

ISCLK

SDIN

*24

*23

*22

ORIG

DFC1

TXP

TXN

H/S

VD+

DGND

OMCK

S/AES

AUDIO

CEN

TCBL

CS8420 Datasheet(PDF) 68 Page - Cirrus Logic

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