CS8420 datasheet(73/80 Pages) CIRRUS

73 / 80 page

CS8420

DS245PP2

The user can configure the interrupt enable register

to cause interrupts to occur whenever “D to E” or

“E to F” buffer transfers occur. This allows deter-

mination of the allowable time periods to interact

with the E buffer.

Also provided are “D to E” and “E to F” inhibit

bits. The associated buffer transfer is disabled

whenever the user sets these bits. These may be

used whenever “long” control port interactions are

occurring. They can also be used to align the be-

havior of the buffers with the selected audio data

flow. For example, if the audio data flow is serial

port in to AES3 out, then it is necessary to inhibit

“D toE” transfers, since these would overwrite the

desired transmit C data with invalid data.

Flowcharts for reading and writing to the E buffer

are shown in Figures 41 and 42. For reading, since

a D to E interrupt just occurred, then there a sub-

stantial time interval until the next D to E transfer

(approximately 192 frames worth of time). This is

usually plenty of time to access the E data without

having to inhibit the next transfer.

For writing, the sequence starts after a E to F trans-

fer, which is based on the output timebase. Since a

D to E transfer could occur at any time (this is

based on the input timebase), then it is important to

inhibit D to E transfers while writing to the E buffer

until all writes are complete. Then wait until the

next E to F transfer occurs before enabling D to E

transfers. This ensures that the data written to the E

buffer actually gets transmitted and not overwritten

by a D to E transfer.

If the channel status block to transmit indicates

PRO mode, then the CRCC byte is automatically

calculated by the CS8420, and does not have to be

written into the last byte of the block by the host

microcontroller.

block 1

block 2

block 3

block 4

block 5

block 1

block 2

block 3

block 4

block 5

Contents of E buffer

Updated at Fsi rate

Contents of F buffer

Updated from E

Output at Fso rate

Fso > Fsi (3/2) Causes blocks 1 and 3 to be transmitted twice

Fso < Fsi (2/3) Causes blocks 3 and 6 to not be transmitted

Contents of E buffer

Updated at Fsi rate

Contents of F buffer

Updated from E

Output at Fso rate

block 1

block 2

block 3

block 4

block 5

block 6

block 7

block 1

block 2

block 4

block 5

block 7

Figure 40. Channel Status Block Handling When Fso is Not Equal to Fsi

D to E interrupt occurs

Optionally set D to E inhibit

Read E data

If set, clear D to E inhibit

Return

Figure 41. Flowchart for Reading the E Buffer

E to F interrupt occurs

Optionally set E to F inhibit

Clear D to E inhibit

If set, clear E to F inhibit

Return

Set D to E inhibit

Write E data

Wait for E to F transfer

Figure 42. Flowchart for Writing the E Buffer

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