CS8420 datasheet(24/80 Pages) CIRRUS

24 / 80 page

CS8420

DS245PP2

AES/SPDIF/IEC60958 Transmitter and Receiver

Components” on page 70.

9.6

Mono Mode Operation

Currently, the AES3 standard is being updated to

include options for 96 kHz sample rate operation.

One method is to double the frame rate of the cur-

rent format. This results in a 96 kHz sample rate,

stereo signal carried over a single twisted pair ca-

ble. An alternate method is where the 2 sub-frames

in a 48 kHz frame rate AES3 signal are used to car-

ry consecutive samples of a mono signal, resulting

in a 96 kHz sample rate stream. This allows older

equipment, whose AES3 transmitters and receivers

are not rated for 96 kHz frame rate operation, to

handle 96 kHz sample rate information. In this

“mono mode”, 2 AES3 cables are needed for stereo

data transfer. The CS8420 offers mono mode oper-

ation, both for the AES3 receiver and for the AES3

transmitter. Figure 23 shows the operation of mono

mode in comparison with normal stereo mode. The

receiver and transmitter sections may be indepen-

dently set to mono mode via the MMR and MMT

control bits.

The receiver mono mode effectively doubles Fsi

compared to the input frame rate. The clock output

on the RMCK pin tracks Fsi, and so is doubled in

frequency compared to stereo mode. In mono

mode, A and B sub-frames are routed to the SRC

inputs as consecutive samples.

When the transmitter is in mono mode, either A or

B SRC consecutive outputs are routed alternately

to A and B sub-frames in the AES3 output stream.

Which channel status block is transmitted is also

selectable.

For the AES3 input to serial audio port output data

flow, in receiver mono mode, then the receiver will

TCBL

in or out

VLRCK

Tsetup = >7.5% AES3 frame time

Thold = 0

AES3 Transmitter in Stereo Mode

Tsetup = >15% AES3 frame time

Thold = 0

AES3 Transmitter in Mono Mode

TCBL

in or out

VLRCK

Input

Tsetup

Thold

CUV

C, U, V

Input

Tsetup

Thold

VLRCK is a virtual word clock, which may not exist, but is used to illustrate the CUV timing.

VLRCK duty cycle is 50%.

In stereo mode, VLRCK = AES3 frame rate. In mono mode, VLRCK = 2*AES3 frame rate

If the serial audio output port is in master mode, and TCBL is an output, and the SRC is not in use,

then VLRCK = OLRCK.

If the serial audio input port is in master mode, and TCBL is an input, and the SRC is not between

the serial audio input port and the AES3 transmitter, then VLRCK = ILRCK.

Otherwise, VLRCK needs to be externally created, if required

Figure 22. AES3 Transmitter Timing for C, U and V pin input data

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