CS8420 datasheet(40/80 Pages) CIRRUS

40 / 80 page

CS8420

DS245PP2

11.15 Receiver Error (16) (Read Only)

This register contains the AES3 receiver and PLL status bits. Unmasked bits will go high on occur-

rence of the error, and will stay high until the register is read. Reading the register resets all bits to 0,

unless the error source is still true. Bits that are masked off in the receiver error mask register will

always be 0 in this register. This register defaults to 00.

QCRCQ-subcode data CRC error has occurred. Updated on Q-subcode block boundaries.

0 - No error

1 - Error

CCRCChannel Status Block Cyclic Redundancy Check bit. Updated on CS block boundaries.

This bit is valid in professional mode only.

0 - No error

1 - Error

UNLOCK

PLL lock status bit. Updated on CS block boundaries.

0 - PLL locked

1 - PLL out of lock

Received AES3 Validity bit status. Updated on sub-frame boundaries.

0 - Data is valid and is normally linear coded PCM audio

1 - Data is invalid, or may be valid compressed audio

CONF

Confidence bit. Updated on sub-frame boundaries.

0 - No error

1 - Confidence error. This indicates that the received data eye opening is less than

half a bit period, indicating a poor link that is not meeting specifications.

BIP

Bi-phase error bit. Updated on sub-frame boundaries.

0 - No error

1 - Bi-phase error. This indicates an error in the received bi-phase coding.

PAR

Parity bit. Updated on sub-frame boundaries.

0 - No error

1 - Parity error

11.16 Receiver Error Mask (17)

The bits in this register serve as masks for the corresponding bits of the Receiver Error Register. If a

mask bit is set to 1, the error is considered unmasked, meaning that its occurrence will appear in the

receiver error register, will affect the RERR pin, will affect the RERR interrupt, and will affect the cur-

rent audio sample according to the status of the HOLD bit. If a mask bit is set to 0, the error is con-

sidered masked, meaning that its occurrence will not appear in the receiver error register, will not

affect the RERR pin, will not affect the RERR interrupt, and will not affect the current audio sample.

The CCRC and QCRC bits behave differently from the other bits: they do not affect the current audio

sample even when unmasked. This register defaults to 00.

3210

QCRC

CCRC

UNLOCK

CONF

BIP

PAR

3210

QCRCM

CCRCM

UNLOCKM

CONFM

BIPM

PARM

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