CS8420 datasheet(19/80 Pages) CIRRUS

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CS8420

DS245PP2

AES3 TRANSMITTER AND

RECEIVER

The CS8420 includes an AES3 type digital audio

receiver and an AES3 type digital audio transmit-

ter. A comprehensive buffering scheme provides

read/write access to the channel status and user da-

ta. This buffering scheme is described in the Ap-

pendix: Channel Status and User Data Buffer

Management on page 72.

7.1

AES3 Receiver

The AES3 receiver accepts and decodes audio and

digital data according to the AES3, IEC60958

(S/PDIF), and EIAJ CP-1201 interface standards.

The receiver consists of a differential input stage,

accessed via pins RXP and RXN, a PLL based

clock recovery circuit, and a decoder which sepa-

rates the audio data from the channel status and

user data.

External components are used to terminate and iso-

late the incoming data cables from the CS8420.

These components are detailed in the Appendix

“External AES/SPDIF/IEC60958 Transmitter and

Receiver Components” on page 70.

7.1.1

PLL, Jitter Attenuation, and

Varispeed

An on-chip Phase Locked Loop (PLL) is used to re-

cover the clock from the incoming data stream. Al-

though the on-chip sample rate converter is

immune to large amounts of jitter, there are some

applications where low jitter in the recovered

clock, presented on the RMCK pin, is important.

For this reason, the PLL has been designed to have

good jitter attenuation characteristics, shown in

Figures 18, 19 & 20. In addition, the PLL has been

designed to only use the preambles of the AES3

stream to provide lock update information to the

PLL. This results in the PLL being immune to data

dependent jitter affects, since the AES3 preambles

do not vary with the data. The PLL has the ability

to lock onto a wide range of input sample rates,

with no external component changes. If the sample

rate of the input subsequently changes, for example

in a varispeed application, then the PLL will only

track up to ±12.5% from the nominal center sample

rate. The nominal center sample rate is the sample

rate that the PLL first locks onto upon application

of an AES3 data stream, or after enabling the

CS8420 clocks by setting the RUN control bit. If

the 12.5% sample rate limit is exceeded, the PLL

will return to its wide lock range mode, and re-ac-

quire a new nominal center sample rate.

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