CS8420 datasheet(48/80 Pages) CIRRUS

48 / 80 page

CS8420

DS245PP2

OSCLK - Serial Audio Output Port Bit Clock input or output

Serial bit clock for audio data on the SDOUT pin.

OLRCK - Serial Audio Output Port Left/Right Clock input or output

Word rate clock for the audio data on the SDOUT pin. The frequency will be at the output sample rate

(Fso)

AES3/SPDIF Transmitter Interface:

TCBL - Transmit Channel Status Block Start

This pin can be configured as an input or output. When operated as output, TCBL is high during the first

sub-frame of a transmitted channel status block, and low at all other times. When operated as input,

driving TCBL high for at least three OMCK (or RMCK, depending on which clock is operating the AES3

encoder block) clocks will cause the next transmitted sub-frame to be the start of a channel status

block.

TXN, TXP - Differential Line driver outputs

Differential line driver outputs, transmitting AES3 type data. Drivers are pulled to low while the CS8420

is in the reset state.

Control Port Signals:

SCL/CCLK - Control Port clock

SCL/CCLK is the serial control interface clock, and is used to clock control data bits into and out of the

CS8420.

AD0/CS - Address Bit 0 (I2C) / Control Port Chip Select (SPI)

A falling edge on this pin puts the CS8420 into SPI control port mode. With no falling edge, the CS8420

defaults to I2C mode. In I2C mode, AD0 is a chip address pin. In SPI mode, CS is used to enable the

control port interface on the CS8420.

AD1/CDIN - Address Bit 1 (I2C) / Serial Control data in (SPI)

In I2C mode, AD1 is a chip address pin. In SPI mode, CDIN is the input data line for the control port

interface

SDA/CDOUT - Serial Control Data I/O (I2C) / data out (SPI)

In I2C mode, SDA is the control I/O data line. SDA is open drain, and requires an external pull-up

resistor to VD+. In SPI mode, CDOUT is the output data from the control port interface on the CS8420.

Miscellaneous pins:

U - User Data

The U pin may optionally be used to input User data for transmission by the AES3 transmitter, see

Figure 22 for timing information. Alternatively, the U pin may be set to output User data from the AES3

receiver, see Figure 21 for timing information. If not driven, a 47k

Ω pull-down resistor is recommended

for the U pin, since the default state of the UD direction bit sets the U pin as an input. The pull-down

resistor ensures that the transmitted user data will be zero. If the U pin is always set to be an output,

thereby causing the U bit manager to be the source of the U data, then the resistor is not necessary.

The U pin should not be tied directly to ground, in case it is programmed to be an output, and

subsequently tries to output a logic high. This situation may affect the long term reliability of the device.

If the U pin is driven by a logic level output, then a 100

Ω series resistor is recommended.

CS8420 Datasheet(PDF) 48 Page - Cirrus Logic

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