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PM5347 Datasheet(PDF) 174 Page - PMC-Sierra, Inc |
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PM5347 Datasheet(HTML) 174 Page - PMC-Sierra, Inc |
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174 / 302 page ![]() PM5347 S/UNI-PLUS DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 158 Register 0x49: TPOP Path Status Bit Type Function Default Bit 7 R/W FEBE[3] 0 Bit 6 R/W FEBE[2] 0 Bit 5 R/W FEBE[1] 0 Bit 4 R/W FEBE[0] 0 Bit 3 R/W PRDI 0 Bit 2 R/W APRDI 0 Bit 1 R/W G1[1] 0 Bit 0 R/W G1[0] 0 This register allows control over the path status byte. G1[1], G1[0]: The G1[1:0] bits are inserted in the unused bit positions in the path status byte when the SRCG1 bit of the TPOP Source Control Register is logic zero and primary input TPOHEN is low during the unused bit positions in the path overhead input stream, TPOH. APRDI: The APRDI bit controls the insertion of the auxiliary path remote defect indication. When APRDI is a logic one, the APRDI bit position in the path status byte is set high. When APRDI is a logic zero, the APRDI bit position in the path status byte is set low. This bit has no effect if the SRCG1 bit of the TPOP Source Control Register is logic one or primary input TPOHEN is high during the path status remote defect indication bit position in the path overhead input stream in which case the value is inserted from TPOH. PRDI: The PRDI bit controls the insertion of the path remote defect indication. This register bit value is logically ORed with the input TPRDI. When PRDI is a logic one, the PRDI bit position in the path status byte is set high. When PRDI is a logic zero, the PRDI bit position in the path status byte is set low. This bit has no effect if the SRCG1 bit of the TPOP Source Control Register is logic one or primary input TPOHEN is high during the path status remote |
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