PM5347 datasheet(181/302 Pages) PMC

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PM5347 S/UNI-PLUS

DATA SHEET

PMC-941033

ISSUE 6

SATURN USER NETWORK INTERFACE PLUS

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

165

cells are passed to the receive FIFO regardless of errors detected in the

HCS, and the HCS verification finite state machine never exits the correction

mode. Regardless of the programming of this bit, cells are always dropped

while the cell delineation state machine is in the 'HUNT' or 'PRESYNC' states.

DISCOR:

The DISCOR bit disables the HCS error correction algorithm. When DISCOR

is a logic zero, the error correction algorithm is enabled, and single-bit errors

detected in the cell header are corrected. When DISCOR is a logic one, the

error correction algorithm is disabled, and any error detected in the cell

header is treated as an uncorrectable HCS error.

PASS:

The PASS bit controls the function of the cell filter. When PASS is a logic

zero, cells which match the header cell filter and which have VPI and VCI

fields set to 0 are dropped. When PASS is a logic one, the match header

pattern registers are ignored and filtering of cells with VPI and VCI fields set

to 0 is not performed. The default state of this bit together with the default

states of the bits in the Match Mask and Match Pattern registers enable the

dropping of cells containing all zero VCI and VPI fields.

RXPTYPE:

The RXPTYPE bit selects even or odd parity for outputs RXPRTY[1:0]. When

RXPTYPE is a logic one, even parity is calculated for the output data on

RDAT[15:0]; conversely, when RXPTYPE is a logic zero, odd parity is

calculated for the output data. When RXPTYPE is set to logic one in word

parity mode, output RXPRTY[1] is the even parity bit for outputs RDAT[15:0].

When RXPTYPE is set to logic zero in word parity mode, output RXPRTY[1]

is the odd parity bit for outputs RDAT[15:0]. In word parity mode, RXPRTY[0]

is held low.

When RXPTYPE is set to logic one in byte parity mode, output RXPRTY[1] is

the even parity bit for outputs RDAT[15:8] and output RXPRTY[0] is the even

parity bit for outputs RDAT[7:0]. When RXPTYPE is a logic zero in byte parity

mode, output RXPRTY[1] is the odd parity bit for outputs RDAT[15:8] and

output RXPRTY[0] is the odd parity bit for outputs RDAT[7:0].

FSEN:

The FSEN bit determines the payload mapping of ATM cells when STS-1

(AU-3) mapping is selected. When FSEN is set to logic one, the S/UNI-PLUS

PM5347 Datasheet(PDF) 181 Page - PMC-Sierra, Inc

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