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PM5347 Datasheet(PDF) 201 Page - PMC-Sierra, Inc

Part # PM5347
Description  SATURN USER NETWORK INTERFACE PLUS
PDF  302 Pages
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Manufacturer  PMC [PMC-Sierra, Inc]
Direct Link  http://www.pmc-sierra.com
Logo PMC - PMC-Sierra, Inc

PM5347 Datasheet(HTML) 201 Page - PMC-Sierra, Inc

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PM5347 S/UNI-PLUS
DATA SHEET
PMC-941033
ISSUE 6
SATURN USER NETWORK INTERFACE PLUS
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
185
Register 0x63: TACP FIFO Control
Bit
Type
Function
Default
Bit 7
R/W
TXPTYPE
0
Bit 6
R/W
TXPRTYE
0
Bit 5
R
TXPRTYI[1]
X
Bit 4
R
TXPRTYI[0]
X
Bit 3
R/W
FIFODP[1]
0
Bit 2
R/W
FIFODP[0]
0
Bit 1
R/W
TCALEVEL0
0
Bit 0
R/W
HCSCTLEB
1
HCSCTLEB:
The HCSCTLEB bit enables the XORing of the HCS Control byte with the
generated HCS before insertion into the transmit stream. When HCSCTLEB
is a logic zero, the HCS Control byte provided in the third word of the 27 word
data structure is XORed with the generated HCS. When HCSCTLEB is a
logic one, the HCS Control byte is ignored.
TCALEVEL0:
The TCALEVEL0 bit controls the function of the TCA output. When
TCALEVEL0 is a logic one, a high to low transition on output TCA indicates
that the transmit FIFO is full. When TCALEVEL0 is a logic zero, a high to low
transition on output TCA indicates that the transmit FIFO is almost full and
can accept no more than four additional writes. Refer to the Drop Side
Transmit Interface timing diagram in the Functional Timing section.
FIFODP[1:0]:
The FIFODP[1:0] bits determine the transmit FIFO cell depth. FIFO depth
control is important in systems where the cell latency through the transmit
FIFO must be minimized. When the FIFO is filled to the specified depth, the
transmit cell available signal, TCA transitions to logic zero. The selectable
FIFO cell depths are shown below:



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