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PM5347 Datasheet(PDF) 151 Page - PMC-Sierra, Inc |
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PM5347 Datasheet(HTML) 151 Page - PMC-Sierra, Inc |
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151 / 302 page ![]() PM5347 S/UNI-PLUS DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 135 Register 0x33: RPOP Interrupt Enable Bit Type Function Default Bit 7 R/W PSLE 0 Bit 6 R/W Reserved 0 Bit 5 R/W LOPE 0 Bit 4 R/W Reserved 0 Bit 3 R/W PAISE 0 Bit 2 R/W PRDIE 0 Bit 1 R/W BIPEE 0 Bit 0 R/W FEBEE 0 This register allows interrupt generation to be enabled for path level alarm and error events. FEBEE: The FEBEE bit is the interrupt enable for path FEBEs. When FEBEE is a logic one, an interrupt is generated when a path FEBE is detected. BIPEE: The BIPEE bit is the interrupt enable for path BIP-8 errors. When BIPEE is a logic one, an interrupt is generated when a B3 error is detected. PRDIE: The PRDIE bit is the interrupt enable for path RDI. When PRDIE is a logic one, an interrupt is generated when the path RDI state changes. PAISE: The PAISE bit is the interrupt enable for path AIS. When PAISE is a logic one, an interrupt is generated when the path AIS state changes. LOPE: The LOPE bit is the interrupt enable for LOP. When LOPE is a logic one, an interrupt is generated when the LOP state changes. |
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