LAN88730 datasheet(34/82 Pages) MICROCHIP

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LAN88730

DS60001256B-page 34

 2012-2015 Microchip Technology Inc.

When in EDPD mode, the device’s NLP characteristics may be modified. The device can be configured to transmit NLPs

in EDPD via the EDPD TX NLP Enable bit of the EDPD NLP/Crossover TimeRegister. When enabled, the TX NLP time

interval is configurable via the EDPD TX NLP Interval Timer Select field of the EDPD NLP/Crossover TimeRegister.

When in EDPD mode, the device can also be configured to wake on the reception of one or two NLPs. Setting the EDPD

RX Single NLP Wake Enable bit of the EDPD NLP/Crossover TimeRegister will enable the device to wake on reception

of a single NLP. If the EDPD RX Single NLP Wake Enable bit is cleared, the maximum interval for detecting reception

of two NLPs to wake from EDPD is configurable via the EDPD RX NLP Max Interval Detect Select field of the EDPD

NLP/Crossover TimeRegister.

3.8.4

ISOLATE MODE

The device data paths may be electrically isolated from the MII/RMII interface by setting the Isolate bit of the Basic Con-

trol Register to “1”. In isolation mode, the transceiver does not respond to the TXD, TXEN and TXER inputs, but does

respond to management transactions.

Isolation provides a means for multiple transceivers to be connected to the same MII/RMII interface without contention.

By default, the transceiver is not isolated (on power-up (Isolate =0).

3.8.5

RESETS

The device provides two forms of reset: hardware and software. The device registers are reset by both hardware and

software resets. Select register bits, indicated as “NASR” in the register definitions, are not cleared by a software reset.

The registers are not reset by the power-down modes described in Section 3.8.3.

3.8.5.1

Hardware Reset

A hardware reset is asserted by driving the nRST input pin low. When driven, nRST should be held low for the minimum

time detailed in Section 5.7.3, "Power-On nRST & Configuration Strap Timing" to ensure a proper transceiver reset.

During a hardware reset, an external clock must be supplied to the XTAL1/CLKIN signal.

3.8.5.2

Software Reset

A Software reset is activated by setting the Soft Reset bit of the Basic Control Register to “1”. All registers bits, except

those indicated as “NASR” in the register definitions, are cleared by a Software reset. The Soft Reset bit is self-clearing.

Per the IEEE 802.3u standard, clause 22 (22.2.4.1.1) the reset process will be completed within 0.5 s from the setting

of this bit.

3.8.6

CARRIER SENSE

The carrier sense (CRS) is output on the CRS pin in MII mode, and the CRS_DV pin in RMII mode. CRS is a signal

defined by the MII specification in the IEEE 802.3u standard. The device asserts CRS based only on receive activity

whenever the transceiver is either in repeater mode or full-duplex mode. Otherwise the transceiver asserts CRS based

on either transmit or receive activity.

The carrier sense logic uses the encoded, unscrambled data to determine carrier activity status. It activates carrier

sense with the detection of 2 non-contiguous zeros within any 10 bit span. Carrier sense terminates if a span of 10 con-

secutive ones is detected before a /J/K/ Start-of Stream Delimiter pair. If an SSD pair is detected, carrier sense is

asserted until either /T/R/ End–of-Stream Delimiter pair or a pair of IDLE symbols is detected. Carrier is negated after

the /T/ symbol or the first IDLE. If /T/ is not followed by /R/, then carrier is maintained. Carrier is treated similarly for IDLE

followed by some non-IDLE symbol.

3.8.7

COLLISION DETECT

A collision is the occurrence of simultaneous transmit and receive operations. The COL output is asserted to indicate

that a collision has been detected. COL remains active for the duration of the collision. COL is changed asynchronously

to both RXCLK and TXCLK. The COL output becomes inactive during full duplex mode.

Note:

For the first 16 µs after coming out of reset, the MII/RMII interface will run at 2.5 MHz. After this time, it will

switch to 25 MHz if auto-negotiation is enabled.

Note:

A hardware reset (nRST assertion) is required following power-up. Refer to Section 5.7.3, "Power-On

nRST & Configuration Strap Timing" for additional information.

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