LAN88730 datasheet(64/82 Pages) MICROCHIP

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LAN88730

DS60001256B-page 64

 2012-2015 Microchip Technology Inc.

5.7.2

POWER SEQUENCE TIMING

This diagram illustrates the device power sequencing requirements. The VDDIO, VDD1A, VDD2A and magnetics power

supplies can turn on in any order provided they all reach operational levels within the specified time period tpon. Device

power supplies can turn off in any order provided they all reach 0 volts within the specified time period tpoff.

It is acceptable for the VDD1A/VDD2A supply to remain powered up while the VDDIO supply is at zero volts for a period

not to exceed 750 ms. In this case, nRESET must be asserted while VDDIO is off, and must remain asserted for a min-

imum of 50 ms after the VDDIO supply reaches operational level. Additionally, VDDIO must come up with or after the

VDD1A/VDD2A supply. Configuration straps must meet the requirements specified in Section 5.7.3, "Power-On nRST

& Configuration Strap Timing".

FIGURE 5-2:

POWER SEQUENCE TIMING

TABLE 5-8:

POWER SEQUENCE TIMING VALUES

Symbol

Description

Min.

Typ.

Max.

Unit

tpon

Power supply turn on time

tpoff

Power supply turn off time

500

VDDIO

Magnetics

Power

tpon

tpoff

VDD1A,

VDD2A

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