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LAN88730 Datasheet(PDF) 67 Page - Microchip Technology |
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LAN88730 Datasheet(HTML) 67 Page - Microchip Technology |
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67 / 82 page  2012-2015 Microchip Technology Inc. DS60001256B-page 67 LAN88730 Note 1: 40 ns for 100BASE-TX operation, 400 ns for 10BASE-T operation. 2: Timing was designed for system load between 10 pF and 25 pF. FIGURE 5-5: MII TRANSMIT TIMING TABLE 5-11: MII TRANSMIT TIMING VALUES Symbol Description Min. Typ. Max. Unit Note tclkp TXCLK period (see Note 1)ns tclkh TXCLK high time tclkp * 0.4 tclkp * 0.6 ns tclkl TXCLK low time tclkp * 0.4 tclkp * 0.6 ns tsu TXD[3:0], TXEN, TXER setup time to rising edge of TXCLK 12.0 ns (see Note 2) thold TXD[3:0], TXEN, TXER hold time after rising edge of TXCLK 0ns (see Note 2) t1 TXCLK rising edge after TXEN assertion to RXDV assertion (100 Mbps internal loopback mode) 160 162 ns (see Note 2) tsu tclkh tclkl tclkp thold tsu thold thold tsu thold TXCLK (OUTPUT) TXD[3:0] (INPUTS) TXEN, TXER (INPUTS) |
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