LAN88730 datasheet(35/82 Pages) MICROCHIP

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DS60001256B-page 35

LAN88730

The COL may be tested by setting the Collision Test bit of the Basic Control Register to “1”. This enables the collision

test. COL will be asserted within 512 bit times of TXEN rising and will be de-asserted within 4 bit times of TXEN falling.

3.8.8

LINK INTEGRITY TEST

The device performs the link integrity test as outlined in the IEEE 802.3u (clause 24-15) Link Monitor state diagram. The

link status is multiplexed with the 10 Mbps link status to form the Link Status bit in the Basic Status Register and to drive

the LINK LED (LED1).

The DSP indicates a valid MLT-3 waveform present on the RXP and RXN signals as defined by the ANSI X3.263 TP-

PMD standard, to the Link Monitor state-machine, using the internal DATA_VALID signal. When DATA_VALID is

asserted, the control logic moves into a Link-Ready state and waits for an enable from the auto-negotiation block. When

received, the Link-Up state is entered, and the Transmit and Receive logic blocks become active. Should auto-negoti-

ation be disabled, the link integrity logic moves immediately to the Link-Up state when the DATA_VALID is asserted.

To allow the line to stabilize, the link integrity logic will wait a minimum of 330 ms from the time DATA_VALID is asserted

until the Link-Ready state is entered. Should the DATA_VALID input be negated at any time, this logic will immediately

negate the Link signal and enter the Link-Down state.

When the 10/100 digital block is in 10BASE-T mode, the link status is derived from the 10BASE-T receiver logic.

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LAN88730 Datasheet(PDF) 35 Page - Microchip Technology