LAN9117 datasheet(97/114 Pages) MICROCHIP

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 2005-2016 Microchip Technology Inc.

DS00002267A-page 97

LAN9117

6.2

PIO Reads

PIO reads can be used to access CSRs or RX Data and RX/TX status FIFOs. In this mode, counters in the CSRs are

latched at the beginning of the read cycle. Read data is valid as indicated in the timing diagram. PIO reads can be per-

formed using Chip Select (nCS) or Read Enable (nRD). Either or both of these control signals must go high between

cycles for the period specified.

TABLE 6-2:

READ AFTER READ TIMING RULES

After Reading...

Wait for this Many ns…

or Perform this Many Reads of

BYTE_TEST…

(Assuming Tcycle of 45ns)

Before Reading...

RX Data FIFO

135

RX_FIFO_INF

RX Status FIFO

135

RX_FIFO_INF

TX Status FIFO

135

TX_FIFO_INF

RX_DROP

180

RX_DROP

Note:

Some registers have restrictions on the timing of back-to-back, write-read and read-read cycles.

FIGURE 6-1:

LAN9117 PIO READ CYCLE TIMING

Note:

The “Data Bus” width is 16 bits.

TABLE 6-3:

PIO READ TIMING

Symbol

Description

MIN

TYP

MAX

Units

tcycle

Read Cycle Time

tcsl

nCS, nRD Assertion Time

tcsh

nCS, nRD Deassertion Time

tcsdv

nCS, nRD Valid to Data Valid

tasu

Address Setup to nCS, nRD Valid

tah

Address Hold Time

tdon

Data Buffer Turn On Time

tdoff

Data Buffer Turn Off Time

tdoh

Data Output Hold Time

Data Bus

nCS, nRD

A[7:1]

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