LAN9117 datasheet(98/114 Pages) MICROCHIP

98 / 114 page

LAN9117

DS00002267A-page 98

 2005-2016 Microchip Technology Inc.

6.3

PIO Burst Reads

In this mode, performance is improved by allowing up to 16, WORD read cycles back-to-back. PIO Burst Reads can be

performed using Chip Select (nCS) or Read Enable (nRD). Either or both of these control signals must go high between

bursts for the period specified.

Note:

A PIO Read cycle begins when both nCS and nRD are asserted. The cycle ends when either or both nCS

and nRD are deasserted. They may be asserted and deasserted in any order.

FIGURE 6-2:

LAN9117 PIO BURST READ CYCLE TIMING

Note:

The “Data Bus” width is 16 bits.

TABLE 6-4:

PIO BURST READ TIMING

Symbol

Description

MIN

TYP

MAX

Units

tcsh

nCS, nRD Deassertion Time

tcsdv

nCS, nRD Valid to Data Valid

tacyc

Address Cycle Time

tasu

Address Setup to nCS, nRD valid

tadv

Address Stable to Data Valid

tah

Address Hold Time

tdon

Data Buffer Turn On Time

tdoff

Data Buffer Turn Off Time

tdoh

Data Output Hold Time

Note:

A PIO Burst Read cycle begins when both nCS and nRD are asserted. The cycle ends when either or both

nCS and nRD are deasserted. They may be asserted and deasserted in any order.

Data Bus

nCS, nRD

A[7:5]

A[4:1]

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