CDCP1803

1:3 LVPECL CLOCK BUFFER

WITH PROGRAMMABLE DIVIDER

SCAS727B − NOVEMBER 2003 − REVISED FEBRUARY 2004

8

POST OFFICE BOX 655303

f − Frequency − GHz

0.40

0.45

0.50

0.55

0.60

0.65

0.70

0.75

0.80

0.85

0.90

0.1

0.3

0.5

0.7

0.9

1.1

1.3

1.5

LVPECL OUTPUT SWING

vs

FREQUENCY

TA = 25°C

Load = 50

Ω to VDD − 2 V

VDD = 3.6 V

VDD = 3.3 V

VDD = 3 V

Figure 3.

supply current electrical characteristics over recommended operating free-air temperature range

(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

IDD

Supply current

Full load

All outputs enabled and terminated with 50

Ω to

VDD − 2 V on LVPECL outputs, f = 800 MHz for LVPECL

outputs

VDD = 3.3 V

140

mA

IDD

Supply current

No load

Outputs enabled, no output load, f = 800 MHz for LVPECL

outputs

VDD = 3.6 V

90

mA

IDD

Supply current saving per LVPECL

output stage disabled, no load

f = 800 MHz for LVPECL output, VDD = 3.3 V

10

mA

IDDZ

Supply current, tri-state

All outputs 3-state by control logic, f = 0 Hz,

VDD = 3.6 V

0.5

mA