CDCP1803

1:3 LVPECL CLOCK BUFFER

WITH PROGRAMMABLE DIVIDER

SCAS727B − NOVEMBER 2003 − REVISED FEBRUARY 2004

16

POST OFFICE BOX 655303

APPLICATION INFORMATION

device behavior during RESET and control pin switching

output behavior from enabling the device (EN=0

% 1)

In disable mode (EN=0), all output drivers are switched in high-Z mode. The S[0:2] control inputs are also

switched off. In the same mode, all flip-flops are reset. The typical current consumption is below 500

µA.

When the device is enabled again, it takes typically 1

µs for the settling of the reference voltage and currents.

During this time, the outputs Y[0:2] and Y[0:2] drive a high signal. After the settle time, the outputs go into the

low state. Due to the synchronization of each output driver signal with the input clock, the state of the waveforms

after enabling the device looks like shown in Figure 12. The inverting input and output signal is not included.

The Y:/1 waveform is the undivided output driver state.

High-Z

EN

IN

Y:/1

Undefined

Low

High-Z

Y:/2

Undefined

Low

High-Z

Y:/4

Undefined

Low

1

µs

Signal State After the Device is Enabled (IN = Low)

High-Z

EN

IN

Y:/1

Undefined

Low

High-Z

Y:/2

Undefined

Low

High-Z

Y:/4

Undefined

Low

1

µs

Signal State After the Device is Enabled (IN = High)

Undivided State is Valid After the First

Positive Transition of the Input Clock

Figure 12. Waveforms