CDCP1803

1:3 LVPECL CLOCK BUFFER

WITH PROGRAMMABLE DIVIDER

SCAS727B − NOVEMBER 2003 − REVISED FEBRUARY 2004

9

POST OFFICE BOX 655303

130

135

140

145

150

100

300

500

700

900

1100

1300

1500

f − Frequency − MHz

SUPPLY CURRENT

vs

FREQUENCY

3 LVPECL Outputs

(P1) Running

VDD = 3.3 V,

TA = 255C,

50

W to VDD −2 V for LVPECL

Figure 4.

package thermal resistance

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

θJA−1

MLF−24 package thermal resistance,

See Note 1

4-layer JEDEC test board (JESD51−7),

airflow = 0 ft/min

106.6

°C/W

θJA−2

MLF−24 package thermal resistance

with thermal vias in PCB, See Note 1

4-layer JEDEC test board (JESD51−7) with four

thermal vias of 22-mil diameter each,

airflow = 0 ft/min

55.4

°C/W

NOTE 1: It is recommended to provide four thermal vias to connect the thermal pad of the package effectively with the PCB and ensure a good

heat sink.

Example:

calculation of the junction-lead temperature with a 4-layer JEDEC test board using four thermal

vias:

125

°C is not violated)