CDCP1803

1:3 LVPECL CLOCK BUFFER

WITH PROGRAMMABLE DIVIDER

SCAS727B − NOVEMBER 2003 − REVISED FEBRUARY 2004

10

POST OFFICE BOX 655303

control input characteristics over recommended operating free-air temperature range

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

tsu

Setup time, S0, S1, S2, and EN pin before clock IN

25

ns

th

Hold time, S0, S1, S2, and EN pin after clock IN

0

ns

t(disable)

Time between latching the EN low transition and when all

outputs are disabled (how much time is required until the

outputs turn off)

10

ns

t(enable)

Time between latching the EN low-to-high transition and

when outputs are enabled based on control settings (how

much time passes before the outputs carry valid signals)

1

µs

Rpullup

Internal pullup resistor on S[2:0] and EN input

42

60

78

k

Ω

VIH(H)

Three level input high, S0, S1, S2, and EN pin, see Note 1

0.9xVDD

V

VIL(L)

Three level low, S0, S1, S2, and EN pin

0.1xVDD

V

IIH

Input current, S0, S1, S2, and EN pin

VI = VDD

−5

µA

IIL

Input current, S0, S1, S2, and EN pin

VI = GND

38

85

µA

NOTES:

1. Leaving this pin floating automatically pulse the logic level high to VDD through an internal pullup resistor of 60 kΩ.

bias voltage VBB over recommended operating free-air temperature range

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

VBB

Output reference voltage

VDD = 3 V − 3.6 V, IBB = −0.2 mA

VDD − 1.4

VDD − 1.2

V

I − Load − mA

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

−5

0

5

10

15

20

25

30

35

VDD = 3.3 V

vs

LOAD

Figure 5.